Abstract: A multiplexed flip-flop electronic device includes a decoder logic circuit for providing a first switching signal, and a control circuit for receiving a clock signal and for providing a gated clock signal forming a second switching signal. The electronic device further includes a multiplexing circuit having N inputs and an output, and a flip flop circuit. The flip-flop circuit includes a first switching stage connected between the N inputs and the output of the multiplexing circuit, and includes N switches being individually controlled by the first switching signal. A first buffer stage is connected to the output of the multiplexing circuit, and a second switching stage is connected to an output of the first buffer stage. The second switching stage is controlled by the second switching signal. A second buffer stage is connected to an output of the second switching stage.

Abstract: The boost device comprises a charge pump circuit having an input and a main output between which an input stage, an intermediate stage and a main output stage are cascade connected. The charge pump circuit also comprises a stand-by output stage having an input node connected to an output node of said intermediate stage and an output node connected to a stand-by output of the charge pump circuit. The boost device further comprises a phase generator stage having a signal input receiving a suitable clock signal generated by a clock generator stage and output terminals generating phase signals supplied to phase inputs of the charge pump circuit.

Abstract: A method of forming an executable program from a plurality of object code modules, each object code module having section data, a set of relocation instructions and one or more symbols, each symbol having a plurality of attributes associated therewith, wherein said relocation instructions includes a data retrieval instruction having a symbol field identifying a symbol and an attribute field identifying a symbol attribute associated with said identified symbol to be retrieved, the method includes: reading at least one relocation from said set of relocations instruction and where said relocation instruction is a data retrieval instruction, determining the symbol identified by the symbol field and retrieving one of said plurality of symbol attributes associated with said symbol in dependence on the contents of the symbol attributes field of said instruction.

Abstract: The present invention relates to a digital control circuit of the P.I. (Proportional Integral) type, receiving an error signal (Error) at an input terminal (IN1) and adapted to provide, at an output terminal (OUT1), a PWM [Pulse Width Modulated] output signal (PWM Output). The circuit is of a type which comprises at least one analog-to-digital converter (100, 100*) connected to the input terminal (IN) and to the output terminal (OUTI) through at least one integrative/proportional branch (120, 121, 130, 134).

Abstract: A receiver of a frequency-modulated signal is provided. The receiver includes a frequency-transposition unit for lowering the frequency of the frequency-modulated signal, and a digital demodulator for regenerating a digital signal from the frequency-transposed signal. The frequency-transposition unit includes a local oscillator for generating a local oscillator signal used in lowering the frequency of the frequency-modulated signal. The frequency-transposed signal is sampled in the digital demodulator at the rate of a sampling signal, and the sampling signal is generated by the local oscillator of the frequency-transposition unit. In a preferred embodiment, the local oscillator includes at least one frequency-divider circuit that delivers the sampling signal. Also provided is a method for regenerating a digital signal from a frequency-modulated signal.

Abstract: A method and system for laying out and accessing data in a disk drive system. The layout resides in a table in firmware of the disk drive system. The table includes multiple entries or rows, one corresponding to each different area in the disk media. The entry provides information about the range of block addresses in that area including the starting and end block address in the area, and information about the range of physical addresses including the head and the starting and ending cylinder number. A firmware routine finds the appropriate entry in the table and converts the block address to the physical address, or vice versa.

Abstract: Apparatus for re-assembling information cells of messages, comprising a message memory, a message data memory, a location memory, and loading apparatus. The message memory stores each message in blocks that can be different lengths. The message data memory stores, for each message, message data defining a location in message memory, a position in the block, and a length of the block that is to receive the cells of the message. The location memory stores, for each message, an indication of the location of the message data. The loading apparatus receives the cells, and for each cell, accesses location memory to determine the location of message data, stores the cell in the message memory at the indicated location, increments the message data defining the location and the position, and compares the incremented position with the stored length of the block to determine whether the end of the block has been reached.

Abstract: A driver circuit for driving a plasma display panel comprising a plurality of cells arranged in a matrix of lines and columns; comprising a set of driver output stages connected to line or column electrodes to which a first electrode of cells of a same line or a same column are connected, respectively. The driver circuit includes a detection device for detecting a short circuit between two or more of the outputs of the driver output stages. It allows to test for alignment faults in the flexible cable connecting together the driver module housing incorporating the driver circuit and the electrodes of the plasma display panel.

Abstract: A simplified DSCP process makes non-self-aligned floating gate semiconductor memory cells of the FLOTOX EEPROM type as incorporated to a cell matrix having control circuitry associated therewith, wherein each cell has a selection transistor associated therewith. The process includes at least the following steps: growing or depositing a gate dielectric layer of the selection transistor and the cell; tunnel masking to define the tunnel area with a dedicated etching step for cleaning the semiconductor surface; growing the tunnel oxide; depositing and doping the first polysilicon layer poly1.

Abstract: A method of identifying fingerprints, the method including the steps of acquiring a test image formed by a number of test points characterized by different grey levels defining a test surface; determining significant points in the test image; and verifying the similarity between regions surrounding the significant points and corresponding regions of a reference image whose points present different grey levels defining a reference surface. The similarity between the regions is verified by computing the integral norm of portions of the test and reference surfaces; and the integral norm is computed using flash cells programmed with a threshold value correlated to the value of the grey levels in the reference region, by biasing the flash cells with a voltage value correlated to the grey level in the test region, and measuring the charge flowing through the flash cells.

Abstract: A method for the calibration of an RF integrated circuit probe comprising a step to determine the characteristics of the RF transmission lines of the probe by means of a vector network analyzer and standard circuits on silicon substrate. The standard circuits comprise contact pads corresponding by their layout to RF connection pads of the integrated circuits to be tested.

Abstract: A structure and method for creating a contact between a conductive layer and a pad for dissipating electrostatic charges comprising the steps of, forming a pad and a composite insulating layer between and over conductive plates on a substrate, wherein the insulating layer isolates and protects the conductive plates and pad from damage, the insulating layer comprising a dielectric region underlying a conductive layer. A passivation layer is formed over at least a portion of the conductive layer and a photoresist is patterned over at least a portion of the passivation. An opening is etched through the passivation and the insulating layers, wherein the photoresist and the conductive layer serve as masks. Finally, a conductive material is deposited in the opening to form an electrical contact between the pad and the conductive layer.

Abstract: A device for detecting the application of a high voltage signal to an internal node of an integrated circuit includes a high-voltage divider circuit and a threshold detection circuit. The threshold detection circuit receives a signal given by the output of the divider circuit, and provides a threshold crossing detection signal at an output thereof based upon the signal crossing a threshold. The detection circuit is connected between the logic supply voltage and ground, and further includes a negative feedback loop. The negative feedback loop is connected to the output of the divider circuit to limit the voltage build-up of the high voltage signal at the output thereof after the crossing of the detection threshold by the signal.

Abstract: A first-in first-out (FIFO) memory device includes a plurality of memory locations having sequential binary addresses, a write address pointer for sequentially accessing the memory locations to write data therein, and a read address pointer for sequentially accessing the memory locations for reading data therefrom. The method and apparatus add an inverted write binary address of the write address pointer to a read binary address of the read address pointer, add one, and discard the most significant bit (MSB) to define the number of empty memory locations.

Abstract: The present invention relates to a start up circuit for commutation power supplies (PWM) or DC/DC converters and to a commutation type power supply comprising such a start up circuit.

Abstract: A system for controlling and driving an electromagnetic actuator includes a unique operational amplifier in the regulation loop for driving the electromagnetic actuator and for monitoring, during different phases of operation, the current in the actuator and the back electromotive force. The new architecture allows for a considerable reduction of the area of integration of the system as a whole.

Abstract: A level shifter uses a current mirror as a current switch connected to the drains of two oppositely-driven FETs. A switch selectively connects the current mirror to its power supply so that no quiescent DC current flows.

Abstract: A semiconductor memory includes a plurality of memory cells connected to one another to form a matrix of memory cells. A charge pump is connected to the matrix of memory cells. A plurality of controllable connection elements are provided, with each controllable connection element connected between an output terminal of the charge pump and a respective column line. Connected to the output of the charge pump is the series connection of a first element equivalent to a controllable connection element, and a second element equivalent to a memory cell in a predetermined biasing condition. A voltage regulator is connected between the second equivalent element and the input terminal of the charge pump for regulating the output voltage therefrom based upon a voltage present between terminals of the second equivalent element.

Abstract: The compression and coding of digital data pertaining to video sequences of pictures including motion estimation for removing temporal redundance are provided by recognizing the occurrence of a change of a scene to control the prediction computation of the pictures. This control is provided using a forward motion estimation for pictures preceding the change of scene, and using a backward motion estimation for pictures subsequent the change of scene of a given sequence. A change of a scene is reliably detected by checking two distinct indexes. These indexes are based on an average value of a smoothness index of the preestablished number of last processed pictures. The smoothness index of a motion field of each picture is calculated by analyzing the motion vectors for all the macroblocks of a subdivision of the picture, except for the peripheral macroblocks. Spurious detections in the event of noisy pictures, zooming and other situations that may adversely affect either one of the indexes are prevented.

Abstract: An echo cancellation functionality taps a digital transmit signal from a transmit channel for processing through an adaptive filter of an echo channel to generate an echo cancellation signal. The adaptive filter has a transfer function substantially matching an echo transfer function which defines a relationship between the transmit signal and an unwanted echo component corrupting an analog receive signal. The echo cancellation signal is digital-to-analog converted to an analog signal and then subtracted from the analog receive signal to substantially cancel out the unwanted echo component. The echo cancellation functionality may be configured in a training mode to generate an error signal used to adaptively configure the adaptive filter transfer function to substantially match the echo transfer function. When in training mode, certain components of an adaptation loop which contribute to a feedback loop transfer function are selectively by-passed.