Abstract: A microprocessor comprises a central processing unit having an arithmetic and logic unit with two inputs and one input fed-back to one of the inputs through a data path. The arithmetic and logic unit performs arithmetic and logic operations on binary words temporarily stored within registers in the central processing unit. The central processing unit further includes a shift unit in the data path of the arithmetic and logic unit for performing operations to shift bits in the binary words applied thereto. A selection circuit selects a shift operation to be performed. An inverting circuit inverts the ordering of the bits in the binary words applied thereto, which are in the data path of the arithmetic and logic unit, and a selection circuit selects the inversion operation when the latter is required.

Abstract: A chaotic signal generator includes a set of elements connected together for generating chaotic signals. The connection scheme may correspond to the circuit generally referred to as Chua's circuit, particularly when implemented as a cellular neural network. Interposed in the connection scheme is at least one switch, such as a MOS transistor. Opening and closing of the switch causes variation in the chaotic dynamics of the generated signals. A command signal applied to the switch may correspond to a modulating signal for transmission on a channel, such as a high noise channel. The modulating signal may be a binary signal, and the command signal may be a switching signal having a frequency that increases or decreases depending on the logic level of the binary signal.

Abstract: A method of locating packet identifiers held in respective memory locations in a memory, the method comprising receiving a plurality of packets, each packet including a packet identifier, searching said memory locations in a sequence to compare an incoming packet identifier with packet identifiers stored in the memory until a match is found, incrementing one of a set of counters associated respectively with the memory locations, said incremented counter being the one associated with the memory location where the match packet identifier is held, and reading values of each of the counters and using said values to determine the sequence in which the memory locations are searched for subsequent incoming packet identifiers.

Abstract: A method of controlling the quantity and uniformity of distribution of bonded oxygen atoms at the interface between the polysilicon and the monocrystalline silicon includes carrying out, after having loaded the wafer inside the heated chamber of the reactor and evacuated the chamber of the LPCVD reactor under nitrogen atmosphere, a treatment of the wafer with hydrogen at a temperature generally between 500 and 1200° C. and at a vacuum generally between 0.1 Pa and 60000 Pa. The treatment is performed at a time generally between 0.1 and 120 minutes, to remove any and all the oxygen that may have combined with the silicon on the surface of the monocrystalline silicon during the loading inside the heated chamber of the reactor even if it is done under a nitrogen flux. After such a hydrogen treatment, another treatment is carried out substantially under the same vacuum conditions and at a temperature generally between 700 and 1000° C. with nitrogen protoxide (N2O) for a time generally between 0.

Abstract: Described herein is a method for constructing a multipurpose error-control code for multilevel memory cells operating with a variable number of storage levels, in particular for memory cells the storage levels of which can assume the values of the set {ba1, baaa2, . . . , ba1a2. . . ah}, with b, a1, . . . , ah positive integers; the error-control code encoding information words, formed by k q-ary symbols, i.e., belonging to an alphabet containing q different symbols, with q&egr;{ba1, ba1a2, . . . , ba1a2ah}, in corresponding code words formed by n q-ary symbols, with q=ba1a2ah, and having an error-correction capacity t, each code word being generated through an operation of multiplication between the corresponding information word and a generating matrix. The construction method comprises the steps of: acquiring the values of k, t, ba1, ba1a2, . . . , ba1a2. . .

Abstract: A generator circuit for voltage ramps is provided that includes a differential stage with positive feedback coupled between a first and a second voltage reference and having a first output connected to a control terminal of a first output transistor. The first output transistor is connected at an output terminal of the ramp generator circuit to a capacitive charge to be biased with voltage ramps. The ramp generator circuit also includes a second output transistor parallel connected to the first output transistor and having the control terminal connected to a second output of the differential stage.

Abstract: Non-volatile, electrically alterable semiconductor memory, including at least one two-dimensional array of memory cells with a plurality of rows and a plurality of columns, column selection circuitry for selecting columns among the plurality of columns, and a write circuit for simultaneously writing a first number of memory cells. A plurality of doped semiconductor regions is provided, extending transversally to the rows and subdividing a set of memory cells of each row in a corresponding plurality of subsets of memory cells, each subset of memory cells including memory cells of the row formed in a respective doped semiconductor region distinct from the remaining doped semiconductor regions and defining an elementary memory block that can be individually erased.

Abstract: A pulse-controlled analog flip-flop includes a charge element; a charge storage element connected to the charge element; an element for detecting the voltage across the storage element; and an element for discharging the storage element when the detection element has detected that the voltage across the storage element has reached a predetermined threshold.

Abstract: A method for the identification of electronic cards within an investigation zone includes encoding an identification number on M bits distributed into P blocks of Q bits assigned to each electronic card. Reconstruction of the block-by-block identification numbers is performed according to a tree-like iterative algorithm. In this iterative algorithm, each iteration includes a step for transmitting an interrogation message intended for certain electronic cards. Each iteration also includes a step for transmitting, by each of the electronic cards, a response message having a service bit in a narrow time window whose positioning in a sequence of 2Q successive identical windows indicates the value of an as yet unidentified block of bits of its identification number.

Abstract: A synthesizable, synchronous static RAM may include custom built memory cells and a semi-custom input/output/precharge section in bit slice form, a semi-custom built decoder connected to the bit slice, and a semi-custom built control clock generation section connected to the semi-custom built decoder and input/output section. The components may be arranged to provide high speed access, easy testability, and asynchronous initialization capabilities while reducing design time, and in a size that is significantly smaller than existing semi-custom or standard cell based memory designs.

Abstract: A telephone line current amplifier comprises a current amplifying device comprising a first, second and third amplifier connected in cascade. The current from the third amplifier forms the output current of the current amplifying device. The current from the first amplifier subtracts from the current provided by the third amplifier, and the current from the second amplifier operates as a rectifier and outputs its current onto a power supply terminal. The power supply terminal is decoupled from ground via a capacitor. Another embodiment of the telephone line current amplifier comprises only two amplifiers if less severe distortion ratios are imposed.

Abstract: An interleaved memory having an interleaved data path includes an array of memory cells divided into a first bank of memory cells and a second bank of memory cells, first and second arrays of sense amplifiers respectively coupled to the first and second bank of memory cells, and first and second read registers respectively coupled to the first and second arrays of sense amplifiers. A control and timing circuit is connected to the first and second arrays of sense amplifiers and has inputs for receiving externally generated command signals, and outputs for providing path selection signals and a control signal. A third register is connected to the first and second read registers and has inputs for receiving read data therein as a function of the path selection signals. An array of pass-gates are connected to the third register and are controlled in common by the control signal for enabling a transfer of the read data stored in the third register to an array of output buffers.

Abstract: An apparatus (and method) is provided that pumps (up or down) the voltage on a memory cell thereby increasing (above the logic one voltage value) or decreasing (below the logic zero voltage value) the voltage stored in the memory cell, and providing an increased differential on the bit lines during a subsequent read operation of the memory cell. When a logic one or zero voltage is coupled to the first plate of the memory cell for storage, the second plate is held at a voltage that is lower or higher, respectively (preferably a voltage that is the complement logic value of the value being stored). After the word line is deactivated (thereby decoupling the memory cell from the bit line and storing a logic one voltage value or logic zero voltage value), the voltage on the second plate is correspondently either raised or lowered. In the present invention, the second plate is raised or lowered to the precharge and equilibrate value (usually Vdd/2).

Abstract: An integrated device comprises an epitaxial layer forming a first and a second region separated by at least one air gap. The first region forms, for example, a suspended mass of an accelerometer. A bridge element extends on the air gap and has a suspended electrical connection line electrically connecting the first and the second region and a protective structure of etch-resistant material, which surrounds the electrical connection line on all sides. The protective structure is formed by a lower portion of silicon nitride and an upper portion of silicon carbide, the silicon carbide surrounding the electrical connection line at the upper and lateral sides.

Abstract: An apparatus for monitoring a load current drawn by an electrical circuit in a wire includes: 1) a Lorentz force MOS transistor having a first drain current (ID1) and a second drain current (ID2), wherein the Lorentz force MOS transistor is disposed proximate the wire carrying the load current and wherein a magnetic force generated by the load current increases a first current difference between the first drain current and a second drain current; 2) a current difference amplification circuit for detecting the first current difference between the first drain current and the second drain current and generating an amplified output signal; and 3) a current monitoring circuit coupled to the current difference amplification circuit capable of detecting and measuring the amplified output signal.

Abstract: A pre-charging circuit for the output node of an output buffer of an integrated digital system generates a first pulse for enabling the output of new data and a second pulse having a shorter duration than the first pulse for loading the new data in an output data register. The output data register is coupled to the input of the output buffer. A capacitor is connected in parallel to the load capacitance of the output node of the buffer by a pass-gate. The pass-gate is enabled by a pre-charge command corresponding to the logic AND of the second pulse and of the logic XOR of the new data and the data currently present on the output node. A driver is disabled by the first pulse for charging the capacitor to a voltage corresponding to the logic level of data belonging to the group that includes the new data and a logic inversion of the current data.

Abstract: An interface for a data node of a data network including a plurality of data nodes are connected to each other by way of a bus line and activatable in selective manner by address codes transmitted via the bus line. The interface includes an activating address filter allowing addresses intended for the associated data node to be recognized.

Abstract: A method for arbitrating interrupt priorities among peripherals in a microprocessor-based system includes providing a bus which connects a central processing unit (CPU) to a plurality of peripherals and for transmitting a current priority value of the CPU thereon. The method further includes waiting-for activation of an interrupt line connecting all the peripherals and the CPU by the peripherals having a CPU interrupt request priority which is at least equal to, or greater than, the priority of the CPU. The highest priority among the CPU interrupt requests is determined, and the bus is provided with the value of the corresponding interrupt request.

Abstract: A method for performing in a modular arithmetic coprocessor an integer division of a first binary data element by a second binary data element. The result is obtained by making an iterative loop of operations including an integer division of the first data element by a most significant word of the second data element. A test is performed to determine if the result of the division performed corresponds to a word of the final result sought. The first data element is modified by subtracting from it a data element produced by multiplying the second data element by the word of the final result sought that has been previously produced.

Abstract: A method for removing residues of molding material from metal parts of plastic packages of semiconductor devices includes applying first and second pulsed laser radiations to at least one surface region of a metal part covered with residues of molding material. The first pulsed laser radiation has a first wavelength that is absorbed by residues of molding material having a thickness greater than a prescribed thickness. The intensity and the duration of the first pulsed laser radiation causes the residues to be directly attacked. The second pulsed laser radiation has a second wavelength so that residues of molding material having a thickness less than the prescribed value are at least partially transparent and the metal parts are at least partially absorbent. The intensity and the duration of the second pulsed laser radiation causes the formation of plasma at the point of impact with the metal part.