Abstract: The optimized soft programming method is used in a memory consisting of a plurality of cells that are grouped into sectors. The cells that belong to a single sector have gate terminals connected to a plurality of word lines, and drain terminals connected to a plurality of local bit lines. The soft programming method consists of selecting at least one local bit line in the sector, and simultaneously selecting all the word lines in the same sector. A corresponding gate voltage is applied to all the word lines, whereas a constant drain voltage, with a pre-determined value is applied to the local bit line.

Abstract: A rectifying integrator of an input signal with full output dynamics, relative to a voltage reference intermediate with respect to the dynamics of the input signal, includes a first line of integration having at least one integrator for integrating that portion of the input signal that exceeds the voltage reference, and includes a hold capacitor coupled in cascade to the integrator. The rectifying integrator includes a second line of integration, identical to the first line of integration, for integrating that portion of the input signal that remains below the voltage reference. An adder output stage generates an output signal equal to the difference between the voltages existing on the hold capacitors of the first and second lines of integration.

Abstract: An integrated circuit fuse is formed on a substrate by etching a polysilicon, metal or alloy layer deposited thereon to include a central region, at the end of which are zones with electrical contacts. The central region has at least two first electrically parallel arms. A zone of intersection of the first two arms forms a point for focusing a fusing current which facilitates the fusing of the fuse by increasing local current density flowing through the integrated circuit.

Abstract: A process for converting signals in the form of digital data, such as various types of video/audio/data signals for example, between an original format, in which each data item includes a certain number of digits, and a compressed format, in which each data item includes a smaller number of digits. The process includes the operation of associating the data with a configuration including: a first field identifying the number of sub-blocks into which the said certain number of digits are subdivided, a second field that identifies, within the said sub-blocks, respective sections, each one including a given number of digits, and a third field that identifies, for each these sections, one of a plurality of applicable modes (average, compression, transmission “as is”, etc.) that can be adopted for converting the digits in the section between the original format and the compressed format.

Abstract: A preformed adhesive layer for joining components within integrated circuit packaging includes venting slots for controlling the size and location of voids within an assembled integrated circuit package. Air randomly entrapped between the surfaces of the adhesive layer and adjoining components during assembly will generally release into the venting slots during subsequent assembly and/or mounting steps performed at elevated temperatures, rather than creating internal pressures causing separation of package components or releasing into the encapsulant. Die delamination and encapsulant void problems occurring during reflow or other assembly and mounting processes as a result of entrapped air are avoided.

Abstract: A system-on-chip (SOC) includes a power down circuit. Within the SOC are several circuit blocks, each of them operating responsive to a local clock signal. A system clock is coupled to the circuit blocks for providing a system clock signal that functions as the local clock signal for selected circuit blocks. A power control manager provides a signal that at least partially determines whether the system clock will act as the local clock for some of the circuit blocks. Within the circuit blocks is a shutdown circuit that selectively prevents the system clock signal from functioning as the local clock signal in those circuit blocks that receive the shutdown signal, but the shutdown circuit only operates after both the signal to shutdown is received from the power control manager and after the circuit block has, in fact, shutdown.

Abstract: It is described a programming method for a multilevel memory cell able to store a plurality of bits in a plurality of levels. The method comprises the phases of: initially programming a cell threshold value to a first set of levels [0;(m−1)] being m a submultiple of the plurality of levels of the multilevel cell; reprogramming without erasing another set of levels [m;(2m−1)] containing the same number m of levels as the first set; reiterating the reprogramming without erasing phase until the levels of the multilevel cell are exhausted. It is also described a multilevel memory device of the type comprising a plurality of multilevel memory cells organized into sectors, the sectors being themselves split into a plurality of data units wherein a data updating operation is performed in parallel, the data units being programmed by means of the programming method.

Abstract: The method for reading a memory cell includes supplying the cell with a first charge quantity through a capacitive integration element and reintegrating the first charge quantity through a plurality of second charge quantities supplied alternately and in succession to the capacitive integration element. In a first embodiment, the second charge quantities are initially stored in a plurality of capacitive charge-regeneration elements connected alternately and in succession to the capacitive integration element; the second charge quantities are then shared between the capacitive integration element and the capacitive charge-regeneration elements.

Abstract: A circuit estimates speed of an electromagnetic actuator associated with a reading head of a disk storage unit and a digital controller. The circuit includes first and second supply terminals and an output terminal, with the first supply terminal being connected to the electromagnetic actuator. A measuring resistor is connected to the second supply terminal, and is connected in series with the electromagnetic actuator for measuring a current which passes therethrough when a supply voltage is applied between the first and second supply terminals. An adder has an output connected to the output terminal for providing an output voltage, a first input is connected to the first supply terminal, and a second input is connected to the second supply terminal. An adjustable-gain amplifier is connected between the measuring resistor and the second input of the adder for transferring the supply voltage and a voltage across the measuring resistor to the adder.

Abstract: The detection of the presence of a load associated with a power MOS transistor integrated with its control circuit, using a delay determined taking into account the detection with respect to the occurrence of a turn-off control order of the power transistor, and where the filtering time is controlled with the power transistor switching time.

Abstract: Abstract of the Disclosure A monolithically integrated pressure sensor is produced through micromechanical surface structure definition techniques. A microphone cavity in the semiconductor substrate may be monolithically formed by plasma etching the front side or the back side of the silicon wafer to cut a plurality of trenches or holes deep enough to extend for at least part of its thickness into a doped buried layer of opposite type of conductivity of the substrate and of the epitaxial layer grown over it. The method may also include electrochemically etching through such trenches, the silicon of the buried layer with an electrolytic solution suitable for selectively etching the doped silicon of the opposite type of conductivity, thereby making the silicon of the buried layer porous. The method may also include oxidizing and leaching away the silicon so made porous.

Abstract: The method for reading a memory cell is based upon integration in time of the current supplied to the memory cell by a capacitive element. The capacitive element is initially charged and then discharged linearly in a preset time, while the memory cell is biased at a constant voltage. In a first operating mode, initially a first capacitor and a second capacitor are respectively charged to a first charge value and to a second charge value. The second capacitor is discharged through the memory cell at a constant current in a preset time; the first charge is shared between the first capacitor and the second capacitor; and then the shared charge is measured.

Abstract: A transistor includes a substrate region (14) of a first type (P) of conductivity in a semiconductor material layer of the same type (P) of conductivity, at least a first contact region (13) of the first type (P+) of conductivity inside the substrate region (14) and adjacent to a first terminal (C) of the transistor, a well (11) of second type (N) of conductivity placed inside the substrate region (14), wherein the well (11) of second type (N) of conductivity includes at least a second contact region (12) of a second type of conductivity (N+) adjacent to a region of a second terminal (B) of the transistor, and a plurality of third contact regions (10) of the first type of conductivity (P+) adjacent to a plurality of regions of a third terminal (E1, . . . , E3) of the transistor interposed each one (10) and other (12) by proper insulating shapes (20).

Abstract: A phase locked loop is provided that includes a phase comparator, a charge pump circuit, a loop filter, and a voltage controlled oscillator. The charge pump circuit includes two symmetric branches, feedback paths, and circuit breaking switches. Each of the symmetric branches has a constant current generator and a pulsed current generator, with one terminal of the loop filter being connected to one of the symmetric branches and the other terminal of the loop filter being connected to the other of the symmetric branches. The feedback paths control the constant current generators based on voltages at the terminals of the loop filter, and each of the circuit breaking switches couple one of the pulsed current generators and the corresponding terminal of the loop filter. The pulsed current generators supply a first current whose amplitude is proportional to an amplitude of a second current supplied by the constant current generators through the duty cycle of the first current.

Abstract: The invention is directed to a method of manufacturing an area of a first type of conductivity extending a depth into a semiconductor substrate and having a doping gradient as a function of the depth into the semiconductor substrate. The method comprises acts of providing a semiconductor substrate of the first type of conductivity; implanting nitrogen in an upper surface of the semiconductor substrate, with a dose in a range of between approximately 5.1013 and 5.1015 at./cm2, annealing the semiconductor substrate; and growing an epitaxial layer on the substrate of the first type of conductivity having a doping level lower than the semiconductor substrate.

Abstract: A chip of semiconductor material includes a first layer with a first type of conductivity having a surface on the first major surface of the chip, a second layer with the first type of conductivity having a surface on the second major surface of the chip, and a third layer with the first type of conductivity having a resistivity lower than those of the first and second layers and disposed between the first layer and the second layer. A first region with a second, type of conductivity, extends from the first surface into the first layer, and a second region with the second type of conductivity, extends from the second major surface into the second layer. First, second and third electrical connections are provided for connection with the first region, the second region, and the third layer, respectively.

Abstract: A transistor manufacturing process includes the formation, on a layer (15) that will form the base of the transistor, of a stack of an SiGe alloy layer (16), a silicon oxide layer (17) and a silicon nitride layer (18), so as to form in this layer, a false emitter (20), to form, in the layer (15) that will form the base, an extrinsic base region (22) and to siliconize the surface of this extrinsic base region, to cover the extrinsic base region (22) and the false emitter (20) with a silicon dioxide layer (24) which is chemically and mechanically polished down to the level of the false emitter (20), to etch the false emitter (20) in order to form a window (25) and to form, in the window (25) and on the silicon dioxide layer (24), a polysilicon emitter (27). This process has particular application to manufacturing heterojunction bipolar transistors.

Abstract: A current source includes a master branch including a branch current fixing resistor, at least one slave branch, and a current mirror including a mirror transistor in each of the master and slave branches, respectively, to couple the branches. The current source may additionally include at least one of a first circuit for injecting in the current fixing resistor a current proportional to the master branch current and a second circuit for injecting in a degeneration resistor of the mirror transistor of the slave branch a current proportional to a current of the slave branch. The invention is particularly applicable to the manufacture of integrated circuits.

Abstract: An output clock signal is generated from a main clock signal having a predetermined main frequency and from a secondary clock signal generated by a quartz crystal. A frequency synthesizer is preprogrammed to generate two output clock signals whose respective frequencies are slightly greater than and slightly less than the frequency of the main clock signal. The synthesizer switches between the two output clock signals depending on the phase error between the selected output clock signal and the main clock signal.

Abstract: An integrated current reference comprises two current mirrors, the gate source voltage of one of the current mirrors being offset by a voltage reference element, which in an embodiment consists of an on MOSFET.