Abstract: The invention relates to a circuit architecture for processing multi-channel frames of broadband synchronous digital signals, in particular signals of the SONET/SDH standard. The circuit includes an input portion and an output portion. It also contains at least one modular component adapted to process frames comprising a single channel and connectable modularly to N further identical components corresponding to the number of frame channels.

Abstract: This invention relates to a method for manufacturing electronic devices integrated monolithically in a semiconductor substrate delimited by two opposed front and back surfaces of a semiconductor material wafer. The method comprises at least a step of implanting ions of a noble gas, followed by a thermal treatment directed to form gettering microvoids in the semiconductor by evaporation of the gas. The ion implanting step is carried out through the back surface of the semiconductor wafer prior to starting the manufacturing process for the electronic devices, and also can be before the step of cleaning the front surface of the wafer.

Abstract: A method for reducing disturbing effects of coupling between a first transmission/reception device and a second transmission/reception device that are each connected to a subscriber line. According to the method, a signal received on a reception path of the first device is delayed by a delay equal to p times the transmission period. A coupling signal relating to a transmission path of a second device and the reception path of the first device is estimated based on a signal transmitted over the transmission path of the second device, and the delayed signal is ridded of the estimated coupling signal. Additionally, a device for transmitting/receiving a signal is provided. The device includes a memory coupled to a reception path for temporarily storing p symbols, a subtraction circuit, and a coupling estimation block.

Abstract: A process for the integration in a semiconductor chip of an integrated circuit including a high-density integrated circuit components portion and a high-performance logic integrated circuit components portion, providing for: over a semiconductor substrate, insulatively placing a silicidated polysilicon layer that includes a polysilicon layer selectively doped in accordance to a conductivity type of at least the high-performance logic integrated circuit components, covered by a silicide layer; selectively covering the silicidated polysilicon layer with a hard mask; defining gate structures for the high-density integrated circuit components and for the high-performance logic integrated circuit components using said hard mask, the gate structures comprising the silicidated polysilicon layer covered with the hard mask; in a dielectric layer formed over the chip, forming contact openings for electrically contacting the high-density integrated circuit components and the high-performance logic integrated circuit com

Abstract: A microprocessor includes a counter having a counting input and a reset input. The counting input is coupled to a first terminal of the microprocessor for the selection of an operating mode thereof by application of a predetermined number of pulses to the first terminal. The reset input of the counter is driven by a control signal present on a second terminal of the microprocessor. The control signal is maintained by default at a first logic value ensuring the maintaining at zero of the counter during the initialization period by a circuit internal or external the microprocessor. Immunity against electromagnetic perturbations causing the microprocessor to enter into the test mode is provided.

Abstract: A comparator circuit with comparing means for comparing first and second voltages, has current source circuitry for providing current to said comparing means, said current source circuitry having an input for receiving a clock signal having first and second states, whereby the comparing means starts to compare the first and second voltages when the clock signal makes a transition from the first state to the second state; and means for determining when said comparing means has completed a comparison of said first and second voltages and for switching off said current source circuitry and hence said comparing means when said comparison has been completed.

Abstract: A process for manufacturing an integrated device comprises the steps of: forming, in a first wafer of semiconductor material, integrated structures including semiconductor regions and isolation regions; forming, on a second wafer of semiconductor material, interconnection structures of a metal material including plug elements having at least one bonding region of a metal material capable of reacting with the semiconductor regions of the first wafer; and bonding the first and second wafers together by causing the bonding regions of the plug elements to react directly with the semiconductor regions so as to form a metal silicide. Thereby, the metallurgical operations for forming the interconnection structures are completely independent of the operations required for processing silicon, so that there is no interference whatsoever between the two sets of operations.

Abstract: A method of manufacturing an integrated circuit is provided. According to the method, first and second stop layers are deposited on a first dielectric layer that covers a first metallization level. The second stop layer is selectively etched with respect to the first stop layer, and the first stop layer is selectively etched with respect to the first dielectric layer. A second dielectric layer and a third stop layer are deposited. The third stop layer is selectively etched with respect to the second dielectric layer, and the first and second dielectric layers are selectively etched with respect to the stop layers so as to form trenches in the second dielectric layer and holes in the first dielectric layer. Additionally, an integrated circuit is provided that includes first and second metallization levels. A dielectric layer is located between the metallization levels, and a first stop layer is located between the dielectric layer and the second metallization level.

Abstract: A circuit produces a voltage for the erasure or programming of a memory cell. The circuit includes a capacitor, and a discharge circuit connected to a first terminal of the capacitor. The discharge circuit includes a first transistor, a drain of which is connected to the first terminal of the capacitor. The first transistor activates the discharge circuit when a discharge signal is received by a gate of the first transistor. The discharge circuit includes a slow discharge arm and a fast discharge arm parallel-connected to the source of the first transistor. The discharge circuit produces a low discharge current or a high discharge current for discharging the capacitor as a function of an operating mode selection signal.

Abstract: A method for manufacturing a DRAM cell including two active word lines having a drain region and distinct source regions, including, after the forming of insulated conductive lines, the steps of: depositing a first, then a second selectively etchable insulating layers; etching the second insulating layer to only maintain it above conductive lines; depositing and leveling a third insulating layer selectively etchable with respect to at least the second insulating layer; opening the first and third insulating layers to expose the drain region and an insulating trench; filling the previously-formed opening with a conductive material; polishing the entire structure; and depositing a fourth insulating layer, selectively etchable with respect to the third insulating layer.

Abstract: The successive values of the digital symbols which can each take M different possible values are estimated on the basis of the successive values of digital samples each of which results from the combination of at most L successive symbols. This estimation includes a stage by stage progression through a trellis of the Viterbi type with Mk states, with k being less than or equal to L−1. All the states of all the stages are respectively provided with aggregate metrics. When taking into account the sample of rank n, all the transitions arriving at the various states of the current stage of the trellis are partitioned into M groups, each group containing all the transitions arising from the states of the preceding stage which are associated with one of the M possible values of the symbol of rank n−k. The various aggregate metrics are calculated for these various states of the current stage of the trellis.

Abstract: An interleaved memory includes an array of memory cells divided into a first bank of memory cells and a second bank of memory cells. The interleaved memory operates in a burst access mode. A first address counter is coupled to the first bank of memory cells, and an address register is coupled to the first address counter and to the second bank of memory cells. A timing circuit generates increment pulses to the first address counter so that a first random access asynchronous read cycle starts with the first bank of memory cells. A function of an address counter for the second bank of memory cells is being performed by coping contents of the first address counter to the address register.

Abstract: A test signal with given spectral characteristics is injected at input to the quantizer stage of the converter. The same test signal is subjected to cross-correlation with a given signal so as to generate coefficients used for filtering the quantization noise converted into digital form. In this way, a compensation signal is obtained that is applied to the output signal of the quantizer stage jointly with a first compensation signal obtained by applying, to the quantization noise converted into digital form, the same transfer function 28) of the converter. In this way a signal is obtained which, in addition to being used as the global output signal of the converter, is also used for the aforesaid operation of cross-correlation with the test signal.

Abstract: A memory implementing an incremental address counter is sequentially read. An address jump includes detecting an address jump signal, incrementing the incremental address counter, and reading the content of the memory at the incremented address. The content read at the incremented address is transferred into the incremental address counter, and the content of the memory is read at the address contained in the incremental address counter.

Abstract: The converter uses the energy stored in the output filter of a step-down (or buck) converter and in the inductor of a step up/down (or buck-boost) converter to supply a second output of opposite sign. In particular, the converter has a first input receiving an input voltage; a first output supplying a first output voltage of a first sign; a second output supplying a second output voltage of opposite sign; a controlled switch connected between the first input and a first intermediate node; an inductor connected between the first intermediate node and the first output; a diode connected between the first intermediate node and a second intermediate node; and a dual voltage generating circuit connected between the second intermediate node and the second output.

Abstract: A voltage regulator having an output terminal provided for being connected to a load, including an amplifier having its inverting input connected to a reference voltage, and its non-inverting input connected to the output terminal, a charge capacitor arranged between the output terminal and a first supply voltage, first and second voltage-controlled switches each arranged to connect a second supply voltage and the output terminal, and a control means adapted to providing a voltage depending on the output voltage of the amplifier, on the one hand, to the gate of the first switch and, on the other hand, when the current flowing through the first switch reaches a predetermined threshold, to the gate of the second switch.

Abstract: A process for manufacturing components in a multi-layer wafer, including the steps of: providing a multi-layer wafer comprising a first semiconductor material layer, a second semiconductor material layer (, and a dielectric material layer arranged between the first and the second semiconductor material layer; and removing the first semiconductor material layer initially by mechanically thinning the first semiconductor material layer, so as to form a residual conductive layer, and subsequently by chemically removing the residual conductive layer. In one application, the multi-layer wafer is bonded to a first wafer of semiconductor material, with the second semiconductor material layer facing the first wafer, after micro-electromechanical structures have been formed in the second semiconductor material layer of the multi-layer wafer.

Abstract: A high-voltage level shifting circuit with optimized response time, comprising: an inverter having an input and an output, the inverter being connected between a first voltage and a second voltage whose difference remains constant over time; a resistor, in which one terminal is connected to the first voltage and a second terminal is connected to the input of the inverter; a high-voltage transistor, which is connected between the second terminal of the resistor and a current source whose switching on and off determine the level shifting of a digital signal; and a clamp transistor, which is connected between the first voltage and a node that is common to the resistor and to the high-voltage transistor. The gate terminal of the clamp transistor is connected to the output of the inverter.

Abstract: A voltage boosting device having a charge pump circuit formed by a plurality of voltage boosting stages cascade-connected together.

Abstract: A process of fabricating a floating-gate memory device, the process including the steps of: forming a stack of superimposed layers including a floating gate region, a dielectric region, and a control gate region; and forming an insulating layer of oxynitride to the side of the floating gate region to completely seal the floating gate region outwards and improve the retention characteristics of the memory device. The insulating layer is formed during reoxidation of the sides of the floating gate region, after self-align etching the stack of layers and implanting the source/drain of the cell.