Abstract: The invention provides a method and system for performing instructions in a microprocessor having a set of registers, in which instructions which operate on portions of a register are recognized, and “stitching” instructions are inserted into the instruction stream to couple the instructions operating on the portions of the register. The “stitching” parcels are serialized along with other instruction parcels, so that instructions which read from or write to portions of a register can proceed independently and out of their original order, while maintaining the results of that out-or-order operation to be the same as if all instructions were performed in the original order. In a preferred embodiment, the choice of stitching parcels is optimized to the Intel x86 architecture and instruction set.

Abstract: The method comprises the steps of: forming an integrated device including a microactuator in a semiconductor material wafer; forming an immobilization structure of organic material on the wafer; simultaneously forming a securing flange integral with the microactuator and electrical connections for connecting the integrated device to a read/write head; bonding a transducer supporting the read/write head to the securing flange; connecting the electrical connections to the read/write head; cutting the wafer into dices; bonding the microactuator to a suspension; and removing the immobilization structure.

Abstract: A computer system includes on-chip a CPU with an addressable module and a memory interface, the module having packet generating circuitry for event request or control packets, the CPU being operable to generate event request packets, memory access packets or control packets having a common format with packets generated by said module.

Abstract: A cantilevered beam is formed over a cavity to an accurate length by isotropically etching a fast-etching material, such as hydrogen silisquioxane, out of the cavity. The cavity is initially defined within a slow-etching material. The selectivity of the etch rates of the material within the cavity relative to the material defining the walls of the cavity permits accurate control of the length of the free end of the cantilevered beam. The resonant frequency of the cantilevered beam can be tuned to a narrow predetermined range by laser trimming.

Abstract: A device for regulating the amplitude of a chrominance signal includes a variable gain amplifier having an input receiving a sub-carrier signal, and an output providing a regulated sub-carrier signal. The gain of the amplifier is controlled by two regulation loops. The first regulation loop operates during the duration of the reference burst. The second regulation loop operates during the visible line. Each of these loops include an up/down counter controlled by a clock. A digital-analog converter has an input receiving the output signals from the first and second up/down counters. An output signal from the digital-analog converter is connected to the gain control of the amplifier. The digital-analog amplifier is controlled by another clock.

Abstract: An electronic power device is integrated on a substrate of semiconductor material having a first conductivity type, on which an epitaxial layer of the same type of conductivity is grown. The power device comprises a power stage PT and a control stage CT, this latter enclosed in an isolated region having a second type of conductivity type. The power stage PT comprises a first buried area having the second type of conductivity type and a second buried area, partially overlapping the first buried area and having the first conductivity type. The isolation region and the control stage CT comprise respectively a third buried area, having the second conductivity type, and a fourth buried area, partially overlapped to the third buried area and having the first conductivity type. Said first, second, third and fourth buried areas are formed in the epitaxial layers at a depth sufficient to allow the power stage PT and the control stage CT to be entirely formed in the epitaxial layers.

Abstract: The difference between the Vgs voltages of first and second MOS transistors of an integrated circuit due to variations in the production process and/or to variations of other parameters is compensated by a compensation circuit. The compensation circuit includes third and fourth MOS transistors that are the same type as the first and second transistors. These transistors are all formed in the same integrated circuit. The compensation circuit includes a bias circuit for biasing the third and fourth transistors, and a measurement circuit for measuring the difference between the Vgs voltages of the third and fourth transistors. The compensation circuit further includes a current compensation circuit for generating a compensation current that is a function of the difference measured, and a modification circuit for modifying the biasing of the first and second MOS transistor using the compensation current.

Abstract: A pulse programming method for a non-volatile memory device includes: addressing memory cells to be programmed within the device by selecting corresponding hierarchic decoder transistors; biasing the gate terminals of the memory cells; and programming the memory cells by applying a voltage pulse, regulated by a bias circuit, to the drain terminals of the memory cells. Advantageously, the programming method further comprises a step of precharging an internal node of the bias circuit before starting the programming step, the internal node being connected to a parasitic capacitance of the memory device.

Abstract: A device for detecting the pressure exerted at different points of a flexible and/or pliable object that may assume different shapes, includes a plurality of capacitive pressure sensors and at least a system for biasing and reading the capacitance of the sensors. The requirements of flexibility or pliability are satisfied by capacitive pressure sensors formed by two orthogonal sets of parallel or substantially parallel electrodes spaced, at least at each crossing between an electrode of one set and an electrode of the other set, by an elastically compressible dielectric, forming an array of pressure sensing pixel capacitors. The system for biasing and reading the capacitance includes column plate electrode selection circuits and row plate electrode selection circuits and a logic circuit for sequentially scanning the pixel capacitors and outputting pixel values of the pressure for reconstructing a distribution map of the pressure over the area of the array.

Abstract: A reading circuit is provided for reading a memory cell. The reading circuit includes a reference current source, a memory cell biased between its first and second terminals at a predetermined voltage, comparison means for comparing a current flowing in the memory cell with the reference current, and a control gate voltage source coupled to a third terminal of the memory cell. The control gate voltage source includes a virgin memory cell that is biased between two terminals with a voltage of equal value to the biasing voltage of the memory cell. The control gate voltage source produces a control gate voltage at another terminal of the virgin memory cell. In one preferred embodiment, the memory cell and the virgin memory cell are EEPROM cells.

Abstract: The method is for reading a capacitive sensor and may be implemented by a circuit for biasing and reading capacitances that includes circuits for selecting a column line and a row line, and a charge amplifier producing an output voltage representing the capacitance of the selected capacitor intercepted by the selected column and row lines. The method includes preliminarily resetting the output voltage of the charge amplifier, connecting all the deselected row and column plates of the array to a reference voltage and connecting a feedback capacitor and the selected capacitor to an inverting input of the amplifier, applying a step voltage on the capacitor that is connected to the inverting input of the amplifier, and reading the output voltage at steady-state.

Abstract: An architecture for a pipeline processor circuit, preferably of the VLIW type, comprises a plurality of stages and a network of forwarding paths which connect pairs of said stages, as well as a register file for operand write-back. An optimization-of-power-consumption function is provided via inhibition of writing and subsequent readings in said register file of operands retrievable from said forwarding network on account of their reduced liveness length.

Abstract: A processor includes a program memory containing program instructions, and a processor core including several processing units and a central unit. The central unit, upon receipt of a program instruction, issues corresponding instructions to the various processing units. The processor core is clocked by a clock signal. A branching instruction received by the central unit, in the course of a current cycle, is processed in the course of the current cycle.

Abstract: A structure of protection of an area of a semiconductor wafer including a lightly-doped substrate of a first conductivity type against high-frequency noise likely to be injected from components formed in the upper portion of a second area of the wafer. The structure includes a very heavily-doped wall of the first conductivity type having substantially the depth of the upper portion. The wall is divided into segments, each of which is connected to a ground plane.

Abstract: A MOS-gated power device includes a plurality of elementary functional units, each elementary functional unit including a body region of a first conductivity type formed in a semiconductor material layer of a second conductivity type having a first resistivity value. Under each body region a respective lightly doped region of the second conductivity type is provided having a second resistivity value higher than the first resistivity value.

Abstract: Described herein is a nonvolatile memory comprising an input pin receiving an external clock signal supplied by a user; an input buffer receiving the external clock signal and supplying an intermediate clock signal delayed with respect to the external clock signal; and a delay locked loop receiving the intermediate clock signal and supplying an internal clock signal distributed within the nonvolatile memory and substantially in phase with the external clock signal.

Abstract: A neuro-fuzzy filter device that implements a moving-average filtering technique in which the weights for final reconstruction of the signal are calculated in a neuro-fuzzy network according to specific fuzzy rules. The fuzzy rules operate on three signal features for each input sample. The signal features are correlated to the position of the sample in the considered sample window, to the difference between a sample and the sample at the center of the window, and to the difference between a sample and the average of the samples in the window. The filter device for the analysis of a voice signal includes a bank of neuro-fuzzy filters. The signal is split into a number of sub-bands, according to wavelet theory, using a bank of analysis filters including a pair of FIR QMFs and a pair of downsamplers; each sub-band signal is filtered by a neuro-fuzzy filter, and then the various sub-bands are reconstructed by a bank of synthesis filters including a pair of upsamplers, a pair of FIR QMFs, and an adder node.

Abstract: Before a predetermined processing sequence, the integrated circuit detects the state of at least one timer. The circuit controls the activation of the timer if it is not activated, and disables itself if the timer is activated.

Abstract: The integrated semiconductor device includes a first chip of semiconductor material having first, high-voltage, regions at a first high-value voltage; a second chip of semiconductor material having second high-voltage regions connected to the first voltage; and a third chip of semiconductor material arranged between the first chip and the second chip and having at least one low-voltage region at a second, low-value, voltage. A through connection region is formed in the third chip and is connected to the first and second high-voltage regions; through insulating regions surround the through connection region and insulate it from the low-voltage region.

Abstract: Circuitry for adding a first binary number (A) having a plurality of bits (a0, a1, . . . ) to a second binary number (B) having a plurality of bits (b0, b1, . . . ) to produce a third binary number (A+B) having a plurality of bits (s0, s1, . . . ) and/or a fourth binary number (A+B+1) having a plurality of bits (s0′, s1′, . . . ) and corresponding to the addition of the third binary number and one.