Abstract: The transmission of interrupts is described where the interrupt is represented at a peripheral device by the electrical level of a conductor but where it is conveyed to a receiving module by way of a message packet routed along a routing path. According to one aspect, the message packet includes the identification of the peripheral device which generated the interrupt and the receiving module acts on the message packet to implement an interrupt handling routine depending on the identification of the peripheral device. According to another aspect, the message packet includes a transaction identifier which uniquely identifies one of a series of interrupts, and the receiving module generates a response packet containing that transaction identifier thereby allowing the peripheral device to monitor whether or not its interrupts have been treated properly.

Abstract: A method of designing an integrated circuit comprising at least one requester and at least one target, said at least one requester and at least one target being connected by a connection network, said method comprising the steps of defining at least one parameter for said at least one requester to model said requester; defining at least one parameter for said at least one target to model said target; defining connection information for said connection network to model said network; and producing from said defined parameters and connection information implementation information for implementing said system.

Abstract: An analog-to-digital converter (500) for sampling high speed video signals includes a first input (502) for receiving an electronic signal, a sampling clock input (547) for receiving a sampling clock signal, and first and second sampling circuits. The first sampling circuit is arranged in a differential circuit arrangement, and is electrically connected to the first input (502) and to the sampling clock input (547) and is responsive to the sampling clock signal, for sampling the electronic signal to provide a pair of boundary reference voltage signals (706, 708, 710, 712) that bound the voltage of the sampled electronic signal, and further to convert the sampled electronic signal to provide the most significant bits (554) of a digital representation of the electronic signal at times indicated by the sampling clock signal.

Abstract: The integrated microactuator has a stator and a rotor having a circular extension with radial arms which support electrodes extending in a substantially circumferential direction and interleaved with one another. For the manufacture, first a sacrificial region is formed on a silicon substrate; an epitaxial layer is then grown; the circuitry electronic components and the biasing conductive regions are formed; subsequently a. portion of substrate beneath the sacrificial region is removed, forming an aperture extending through the entire substrate; the epitaxial layer is excavated to define and separate from one another the rotor and the stator, and finally the sacrificial region is removed to release the mobile structures from the remainder of the chip.

Abstract: A method of fabricating non-volatile memory devices integrated in a semiconductor substrate is presented. The memory devices include a matrix of non-volatile memory cells, each having floating-gate MOS transistors with associated gate electrodes, as well as control circuitry formed of MOS transistors also having gate electrodes. The method includes forming gate electrodes above the substrate, then depositing a first dielectric layer onto the entire exposed surface. Next the first dielectric layer is etched back to form isolating spacers on the side walls of the gate electrodes of the matrix cells. Then a second dielectric layer is deposited onto the entire exposed surface, and the memory matrix is overlaid with a protective layer. In the circuitry area, the second dielectric layer is etched back to form isolating spacers on the side walls of the gate electrodes of the circuitry transistors, while the floating-gate MOS transistors are protected.

Abstract: A device for detecting a defective power supply connection in an integrated circuit includes a comparison circuit for comparing voltage levels of an input/output pad of the integrated circuit and an internal power supply line connected to a power supply pad of the integrated circuit. A pull-down or pull-up device is connected between the input/output pad and the internal power supply line.

Abstract: An electric connection structure connecting a first silicon body to conductive regions provided on the surface of a second silicon body arranged on the first body. The electric connection structure includes at least one plug region of silicon, which extends through the second body; at least one insulation region laterally surrounding the plug region; and at least one conductive electromechanical connection region arranged between the first body and the second body, and in electrical contact with the plug region and with conductive regions of the first body. To form the plug region, trenches are dug in a first wafer and are filled, at least partially, with insulating material. The plug region is fixed to a metal region provided on a second wafer, by performing a low-temperature heat treatment which causes a chemical reaction between the metal and the silicon. The first wafer is thinned until the trenches and electrical connections are formed on the free face of the first wafer.

Abstract: The sequential access memory array is able to store p words each of n bits. Such p test words each made up of n test bits are written in the memory array, the p test words are extracted sequentially and, for each current word extracted, the n test bits that compose it are compared sequentially with n respective expected data bits before extracting the next test word.

Abstract: A method and a device are provided for reducing the average access time of a non-volatile memory during the reading phase. Reading is effected in either a page mode or a burst mode from a matrix array of memory cells to which recognition logic for recognizing access addresses to the memory is coupled. According to the method, there is provided a buffer memory that is coupled to the matrix array, and a predetermined number of memory words are stored in the buffer memory subsequent to a last-effected reading of the matrix array.

Abstract: The source, drain and channel regions are produced in a silicon layer completely isolated vertically from a carrier substrate by an insulating layer, and are bounded laterally by a lateral isolation region of the shallow trench type.

Abstract: A circuit for biasing the bulk terminal of a first MOS transistor having a first terminal connected to a first line set to a first potential, and a second terminal connected to a second line set to a second potential. The biasing circuit includes a second and a third MOS transistors having first terminals connected respectively to the first line and to the second line, second terminals connected to the bulk terminal of the first MOS transistor, and control terminals connected respectively to the second and to the first line.

Abstract: A voltage converter comprises an input, an output and a current control arrangement for controlling the output current of the voltage converter circuit. The current control arrangement comprises a first mode, when the voltage output by the converter circuit is above a threshold voltage, and a second mode in which the voltage output by the circuit is below the threshold voltage. The first and second modes are controlled by the same current control arrangement. The current control arrangement comprises comparing means arranged to receive a reference voltage wherein the reference voltage is a voltage offset associated with at least one of the inputs of the comparing means.

Abstract: The memory device has hierarchical sector decoding. A plurality of groups of supply lines is provided, one for each sector row, extending parallel to the sector rows. A plurality of switching stages are each connected between a respective sector and a respective group of supply lines; the switching stages connected to sectors arranged on a same column are controlled by same control signals supplied on control lines extending parallel to the columns of sectors. For biasing the sectors, modification voltages are sent to at least one selected group of biasing lines, and control signals are sent to the switching stages connected to a selected sector column.

Abstract: An operational amplifier includes an input stage, and a level-transforming stage with first and second arms. Each arm has at least one bipolar transistor. Input transistors are connected to the input stage and are connected together by their bases. At least one gain stage is connected to the transistor of the second transforming arm. A current terminal of the transistor on the first transforming arm is connected to its base by a bypass arm. In addition, the amplifier has a centering transistor connected by its base to the transistors on the arms of the transforming stage for controlling a current which conducts through the bypass arm.

Abstract: A multilevel memory stores words formed by a plurality of binary subwords in a plurality of cells, each cell having has a respective threshold value. The cells are arranged on cell rows and columns, are grouped into sectors divided into sector blocks, and are selected via a global row decoder, a global column decoder, and a plurality of local row decoders, which simultaneously supply a ramp voltage to a biasing terminal of the selected cells. Threshold reading comparators are connected to the selected cells, and generate threshold attainment signals when the ramp voltage reaches the threshold value of the selected cells; switches, are arranged between the global word lines and local word lines, opening of the switches is individually controlled by the threshold attainment signals, thereby the local word lines are maintained at a the threshold voltage of the respective selected cell, after opening of the switches.

Abstract: A contact opening through an insulating layer is filled with metal and etched back to form a metal plug within the opening. A metal interconnect line can then be formed over the contact, and makes electrical contact with the metal plug. Since the contact opening is filled by the metal plug, it is not necessary for the metal signal line to have a widened portion in order to ensure enclosure.

Abstract: The present invention relates to a method of manufacturing integrated circuits including high and low voltage MOS transistors. This method includes steps of forming insulated gate structure forming lightly-doped drain/source regions, depositing an insulating layer; forming a mask above the gates of the high voltage transistors which extends laterally beyond said gates; etching the insulating layer to leave spacers on the edges of the low voltage transistor gates; implanting a dopant adapted to forming heavily-doped drain/source contact regions of the high and low voltage transistors; and forming in a self-aligned way a metal silicide layer on the drain/source contact regions of all transistors, as well as on the gate contacts of the low voltage transistors.

Abstract: A method is provided for forming an on-screen display (OSD) for overlay on a video image. According to the method, colors that are to be used to display the OSD are stored in a color look-up table, and a coefficient of transparency is assigned to each line of pixels of the OSD before overlaying the OSD on the video image. In a preferred method, the colors are stored in the color look-up table as three significant values representing chrominance and luminance for each pixel of the OSD, and the assigned coefficients of transparency are stored in a programmable register. This provides a substantial memory space gain in the color look-up table, and thus the range of available colors can be very wide. A device for forming an OSD for overlay on a video image is also provided. The device includes a color look-up table that stores a color for each pixel of the OSD, and a transparency programming register that assigns a transparency level to each line of pixels of the OSD.

Abstract: A multi-carrier transmission system such as a DMT system. Channel information is transmitted between two transceivers using a plurality of sub-carriers modulated with symbols, each of which represents a multiplicity of bits. Each of the transceivers includes a receiver and a transmitter in which a fixed maximum value was determined for the number of bits for each symbol and in which the system is adapted to determine the bit capacity per symbol of each of the plurality of sub-carriers and to increase the number of bits represented by a symbol transmitted over those sub-carriers having a capacity less than a fixed maximum value to the maximum value by the addition of channel coding bits. The fixed maximum value for the number of bits for each symbol may be determined on the basis of the bit capacity of that one of the sub-carriers having the highest theoretical bit capacity may be at least as large as the theoretical bit capacity.

Abstract: A radiation hardened memory device includes active gate isolation structures placed in series with conventional oxide isolation regions between the active regions of a memory cell array. The active gate isolation structure includes a gate oxide and polycrystalline silicon gate layer electrically coupled to a voltage potential resulting in an active gate isolation structure that prevents a conductive channel extending from adjacent active regions from forming. The gate oxide of the active gate isolation structures is relatively thin compared to the conventional oxide isolation regions and thus, will be less susceptible to any adverse influence from trapped charges caused by radiation exposure.