Abstract: An integrated circuit includes a sensor that reads a fingerprint and provides data corresponding to the fingerprint to a computation engine coupled to the sensor. The computation engine compares the data to stored data and enables a smart card coupled to the computation engine when the data and the stored data match. The computation engine may include an array of flash memory cells arranged in pairs of rows, where flash memory cells in any one row have sources coupled to a common row line and a plurality of conductance mode neurons each having first and second inputs coupled to first and second row lines forming a respective pair of rows. The neurons are coupled to the flash memory cells through a buffer circuit sets a drain-source voltage of the flash memory cells in the row pair coupled to the neuron.

Abstract: A structure and method is disclosed for dissipating electrostatic charges comprising an underlying dielectric layer disposed over capacitor plates of sensor circuitry, and a conductive layer and passivation layers disposed over the underlying dielectric layer wherein the conductive layer diffuses electrostatic charges at the surface of the integrated circuit.

Abstract: In a method for testing integrated circuits present on a silicon wafer, a full sequence for the test of an integrated circuit comprises a plurality of elementary tests. The test method comprises preliminary steps consisting of the classification of the elementary test steps into statistically essential test steps and statistically secondary test steps and in defining a limited test sequence that comprises only statistically essential elementary test steps. The integrated circuits are then tested by means of a test loop comprising a first test step consisting of the application, to K integrated circuits, of a full test sequence and a second test step consisting of the application, to N following integrated circuits, of a reduced test sequence.

Abstract: An electrical resistor integrated in an integrated semiconductor circuit to have a useful resistor with two spaced-apart useful resistor terminal contact regions and a useful resistor region of semiconductor material located therebetween; and an auxiliary resistor having two spaced-apart auxiliary resistor terminal contact regions and an auxiliary resistor region located therebetween.

Abstract: A method of manufacturing an electronic structure, which structure comprises a first power device and a second unidirectional device, both integrated in the same protective package. The first device having at least first and second electrodes of the first device, with said first electrode of the first device being attached to the package. The second device having first and second electrodes of the second device, wherein the first electrode of the second device is superposed on the second electrode of the first device and connected electrically to the second electrode of the first device.

Abstract: An integrated circuit is provided that includes a substrate incorporating a semiconductor photodiode device having a p-n junction. The photodiode device includes at least one capacitive trench buried in the substrate and connected in parallel with the junction. In a preferred embodiment, the substrate is formed from silicon, and the capacitive trench includes an internal doped silicon region partially enveloped by an insulating wall that laterally separates the internal region from the substrate. Also provided is a method for fabricating an integrated circuit including a substrate that incorporates a semiconductor photodiode device having a p-n junction.

Abstract: A digital signal processor is designed to execute variable-sized instructions that may include up to N elementary instruction codes. The processor comprises a memory program comprising I individually addressable, parallel-connected memory banks in which the codes of a program are recorded in an interlaced fashion, and a circuit for reading the program memory arranged to read a code in each of the I memory banks during a cycle for reading an instruction. A cycle for reading an instruction in the program memory includes reading a sequence of codes that includes the instruction code or codes to be read and can also include codes, belonging to a following instruction, that are filtered before the instruction is applied to execution units. The program memory of the digital signal processor does not include any no-operation type codes.

Abstract: A method of erasing a flash memory integrated in a chip of semiconductor material and including at least one matrix of cells with a plurality of rows and a plurality of columns made in at least one insulated body, the cells of each row being connected to a corresponding word line; the method includes the step of applying a single erasing pulse relative to a selected single one of the at least one body to a selected subset of the word lines for erasing the cells of each corresponding row made in the selected body with no intermediate check of the completion of the erasure.

Abstract: A method for estimating the impulse response of an information transmission channel includes evaluating a useful number of coefficients of an impulse response of the information transmission channel as a function of actual characteristics of the information transmission channel. This evaluation is carried out, for example, by using a time domain spreading parameter of the channel.

Abstract: A memory device having redundancy is disclosed. The memory device includes an array of memory cells organized into rows and columns of memory cells, each row of memory cells including a plurality of addressable memory cells and redundant memory cells, the array of memory cells including row lines and column lines, each row line being coupled to memory cells in a distinct row of memory cells, each column line being coupled to memory cells in a distinct column of memory cells, and column input/output lines. The memory device further includes a redundancy circuitry for selectively coupling column lines to column input/output lines of the array of memory cells and selectively decoupling at least one column line from the column input/output lines, based upon an address value received by the memory device during a memory access operation.

Abstract: A microprocessor may be switchable between a normal mode and a test mode for performing a test program and may include a central processing unit (CPU) for saving contextual data in a stack of the microprocessor at the time of switching to the test mode. The CPU may deliver, at the beginning of the test program and on an input/output port, contextual data present in the stack beginning with the top of the stack. The CPU may also decrement a stack pointer by a value corresponding to a number of contextual data delivered.

Abstract: Data is encoded in a solid state image sensor that includes a sensor pixel array by varying the color processing applied to at least some of the border pixels of the sensor pixel array. Data may be encoded in the color processing by varying the pattern of a color filter mosaic and by varying a pattern of a microlens array in accordance with a predetermined scheme. This scheme includes omission of color filter material and omission of the microlens array from selected pixels. The data, typically encoded in a binary format, is read by illuminating the sensor pixel array and by processing the output signals from the border pixels. The encoded data may include color process codes, mask revision codes and product codes.

Abstract: A programmable logic device may include a programmable interconnect structure and a plurality of configurable logic elements including data latches interconnected by the interconnect structure. At least one of the configurable logic elements may be configurable as both a shift register and a lookup table. Also, the shift register may be enabled to operate as a bi-directional shift register by the inclusion of a first circuit for configuring the data latches either as series-connected inverters during a shift operation or as data latches after each shift operation. A second circuit for selecting a direction of shifting may also be included, as well as a third circuit for supplying data to the input of the shift register as determined by the direction of shifting.

Abstract: A system for relatively rapidly configuring reconfigurable devices with a plurality of latches is provided. The number of clock cycles for loading the configuration data may be reduced by a substantial amount, and the fidelity of data loaded into the configuration latches may be relatively high. The invention also incorporates procedures for configuring multiple reconfigurable devices, which are similar to daisy chaining techniques.

Abstract: A filtering circuit includes circuits for delivering first and second ramp-shaped signals when a logic signal to be filtered changes values, and includes logic circuits each with a switching threshold, for receiving the ramp-shaped signals. A memory unit delivers an output signal having a first value when outputs of the logic circuits have a first pair of values, and delivers a second value when the outputs of the logic circuits have a second pair of values. The filtering circuit may be applied to the filtering of an external clock signal in serial type memory devices.

Abstract: Method for refreshing data stored in an electrically erasable and programmable non-volatile semiconductor memory including at least one two-dimensional array of memory cells containing a plurality of individually erasable and programmable memory pages. Each time a request to modify a content of a memory page is received by the memory, the method provides for modifying the content of said memory page and submitting a portion of the two-dimensional array to a refresh procedure. The refresh procedure includes detecting memory cells of that memory portion that have partially lost a respective datum stored therein and reprogramming the datum in the detected memory cells.

Abstract: A look-up table apparatus is provided for performing two-bit arithmetic operation including carry generation. The look-up table is modified to perform two concurrent combinatorial functions, or one function for an increased number of inputs. The look-up table of the present invention can implement two full adders or subtractors, or two-bit counters, for example. One portion of the modified look-up table provides two bits of a sum output, and another portion of the modified table provides a fast carry out signal for application to a next stage of an adder/subtractor/counter.

Abstract: A method of driving an inductive load connected to an output of a power stage includes comparing a signal representative of an instantaneous value of current flowing through the inductive load with upper and lower thresholds during a switching cycle. The method also includes alternately performing a magnetization phase during which current is forced through the inductive load, and a demagnetization phase during which a load inductance of the inductive load discharges through at least one of a slow recirculation discharge current path and a fast recirculation discharge current path. Switching is performed between the slow and fast recirculation discharge current paths during each switching cycle as a function of the comparison for reducing a ripple on an output signal from the power stage.

Abstract: An image plane includes a plurality of pixels. Each pixel comprises a photodiode and two transistors, and each pixel is connected by a signal bus to a respective storage node located off the image plane. Each storage node comprises two capacitors and associated switches. One of the transistors applies a reset pulse to the pixel, and the other transistor connects the pixel to a given conductor of the signal bus, which is then connected to the storage node. The pixel transistors can be operated simultaneously, and the sensed values can subsequently be transferred from the storage nodes sequentially.

Abstract: A switched mode power supply having a first circuit provided with a primary winding of a transformer to which a pulse voltage is applied, a second circuit having a secondary winding of the transformer, a reactor provided with a magnetic core and which has a terminal connected to a terminal of the secondary winding, at least one filter provided with input and output terminals and a first diode connected in parallel to the input terminals of the filter is shown. The other terminal of the reactor is connected to a terminal of the first diode. The power supply includes a second diode that has a first terminal connected to the other terminal of the first diode and a second terminal connected to the other terminal of the secondary winding and a control circuit coupled to an output terminal of the filter and to the other terminal of the secondary winding. The control circuit generates a current able to reset the magnetic core of the reactor.