Abstract: A circuit includes a differential amplifier that generates a differential offset signal on its output terminals. The circuit also includes an offset compensator that has input terminals respectively coupled to the amplifier output terminals and a compensation terminal coupled to the differential amplifier. The compensator maintains the differential offset signal at a predetermined value, for example 0 V. When used in an integrated read-head preamplifier, such a circuit compensates for the nonzero head bias voltage, i.e., the preamplifier input offset voltage, without using a component that is external to the integrated preamplifier circuit.

Abstract: A method of filtering debugging data in a computer system including at least one central processing unit and a memory unit coupled to the at least one central processing unit.

Abstract: A system for diagnosing a driver and detecting circuit anomalies therein includes: voltage comparator circuits for generating diagnostic logic signals, each of which indicates the existence of a corresponding type of anomaly; and a coding circuit to receive the diagnostic logic signals and to output information relating to an overall operating state of the driver. The coding circuit includes a first portion to provide at its output first logic input signals indicating the last anomaly to occur since a system reset operation. The coding circuit also includes a second portion for coding the first logic input signals. The second portion includes a sequential logic network to receive the first logic input signals and at least one second logic signal indicating the current operating phase of the driver. The second portion provides, as a function of the first and second logic signals, a stable internal state to determine the output information in the form of an N bit coded word.

Abstract: The present invention relates to the positioning of the read/write transducer heads of an hard disk (HD) in a designated landing zone when requested or when the electrical power is removed from the drive. In particularly it relates to the detection of the back electromotive force (BEMF) of the motor involved in the positioning of the read/write transducer heads.

Abstract: A method of forming a doped region in an integrated circuit which includes a matrix of memory cells and lightly-doped drain transistors and which is fabricated by means of a process providing for a Self-Aligned Source masked etch and implant and for a selective salicidation of some doped regions, the doped region suitable for forming an integrated resistor and/or an abrupt-profile source/drain region of a transistor. The doped region is formed by introducing into a semiconductor layer of a first conductivity type a dopant of a second conductivity type and exploiting the SAS masked implant used to form source regions of the matrix of memory cells. At least a portion of a surface of the doped region is prevented from being salicidated by using as a protective mask a portion of a dielectric layer from which insulating sidewall spacers for the LDD transistors are formed.

Abstract: A method for testing a semiconductor memory cell comprising first and second transistors in cross-coupled arrangement to form a bistable latch, the drains of the transistors respectively representing first and second nodes each for storing a high or low potential state, and each node being connected to a respective semiconductor arrangement for replacing charge leaked from the node and to a respective switching means, activatable by a word-line, for coupling the node to a respective bit-line, the method comprising the steps of: connecting the bit-lines to the low potential; activating the word-line to connect the first node to the first bit-line to allow any potential on the first node to fall towards the potential on the first bit-line; and monitoring charge flow from the first node to the first bit-line to test the operation of the first semiconductor arrangement.

Abstract: An A.C./D.C. converter including a filtering capacitor and further including a first branch essentially including a first rectifying circuit and a current limiting circuit; a second branch essentially including a second rectifying circuit, the series voltage drop of which is limited to that of the switches forming it; and a selection circuit for selecting one of the two rectifying circuits.

Abstract: A sensing device having a microelectromechanical structure made of semiconductor material, and a control loop for controlling the microelectromechanical structure, the microelectromechanical structure including a stator element and a rotor element electrostatically coupled together, and the control loop including a position interface supplying a position signal indicative of the position of the rotor element, and a one-bit quantizer receiving the position signal and supplying a corresponding bit sequence. The sensing device further includes a calibration device for calibrating the microelectromechanical structure, including a microactuator made of semiconductor material and coupled to the rotor element, and a driving circuit for driving the microactuator, and receiving the bit sequence and supplying to the microactuator a driving signal correlated to a mean value of the bit sequence in a given time window.

Abstract: It is described a circuit generating a stable reference voltage with respect to temperature, which circuit is connected between first and second voltage references and comprises at least one current generating circuit adapted to inject a reference current into a resistive element connected between a base terminal of a bipolar transistor and an additional voltage reference. The bipolar transistor is connected between the first and second voltage references and to an output terminal of the generator circuit whereat the stable reference voltage with respect to temperature is. The generator circuit further comprises at least another resistive element, feedback connected between the output terminal of the generator circuit and the base terminal of the bipolar transistor to enable injecting additional current, having reverse dependence on temperature from the reference current, into the resistive element.

Abstract: The invention relates to a process for protection of the grid of a transistor in an integrated circuit for production of a local interconnection pad straddling over the grid and the silicon substrate on which it is formed. The process consists of applying a double dielectric-conducting layer on the transistor grid into which a polysilicon layer is added in order to use the selectivity principle, which is large considering the etching of polysilicon with respect to the oxide in which the local interconnection pad is formed. Furthermore, with the process according to the invention, a silicidation treatment can be applied beforehand on the active areas of the transistor and the grid.

Abstract: An amplifier device with gain switching includes an amplifier, and a configurable load circuit including an inductive element. The configurable load circuit is capable of exhibiting two configurations having two different impedance values. A controllable switch is connected between the amplifier and the load circuit to select one of the two configurations of the load circuit. The load circuit includes two insulated-gate field effect load transistors connected in series, and which operate in a triode mode. The inductive element is connected in parallel with the pair of load transistors, and between a power supply terminal and the switching circuit.

Abstract: A microprocessor is for detecting an interrupt request during execution of a program, saving contextual data elements of the program being executed, sending an interrupt acknowledge signal, and jumping to an interrupt subroutine if the interrupt request is still present after saving the contextual data. Otherwise, the microprocessor resumes execution of the interrupted program.

Abstract: The microarchitecture of the arithmetic unit includes two cascaded N bit adders to provide an N bits result in an accumulator. The arithmetic unit also includes a carry save adder, followed by an adder, which, along with the accumulator, are extended to N+1 bits. A circuit for determining the output carry value associated with the result is also provided.

Abstract: A memory device implements a reading operation that comprises:

Abstract: A process for the manufacturing of an integrated circuit including a low operating voltage, high-performance logic circuitry and an embedded memory device having a high operating voltage higher than the low operating voltage of the logic circuitry, providing for: on first portions of a semiconductor substrate, forming a first gate oxide layer for first transistors operating at the high operating voltage; on second portions of the semiconductor substrate, forming a second gate oxide layer for memory cells of the memory device; on the first and second gate oxide layers, forming from a first polysilicon layer gate electrodes for the first transistors, and floating-gate electrodes for the memory cells; forming over the floating-gate electrodes of the memory cells a dielectric layer; on third portions of the semiconductor substrate, forming a third gate oxide layer for second transistors operating at the low operating voltage; on the dielectric layer and on the third portions of the semiconductor substrate, formin

Abstract: A method for storing a plurality of still images to form a panoramic image. The method comprising the steps of receiving a first image forming a part of a series of images to form a panoramic image and storing the first image in memory. When one or more subsequent images after the first image are received the steps of calculating one or more panoramic parameters between a current image and a previous image stored in memory and storing the current image with the one or more panoramic parameters in memory are performed.

Abstract: A variable gain amplifier is described which comprises a first device to which a first control signal (Vc, Vc1) is applied so that the gain (Ai1, Ai) of an output signal (iout, io) of the first device (11, 22, Q45-Q48) with respect to a first input signal (in, i1, ir) is a function of the exponential type of the first control signal (Vc, Vc1). The amplifier comprises a feedback network (25, Q51-Q58) connected between an output terminal and an input terminal of the first device (22, Q45-Q48) so as to assure that the gain (Ai) in decibel of the first device (22, Q45-Q48) is a linear function of the first control signal (Vc1). (FIG.

Abstract: A semiconductor memory cell having a word line, a bit line, a precharge line, an access transistor, and first and second cross-coupled inverters. The first inverter includes a first P-channel transistor and a first N-channel transistor, and the second inverter includes a second P-channel transistor and a second N-channel transistor. The access transistor selectively couples the bit line to an output of the first or second inverter, and one terminal of the first N-channel transistor is connected to the precharge line. In a preferred embodiment, a control circuit is provided that, during a writing operation, supplies data to be written to the memory cell to the bit line, supplies a pulse signal to the precharge line, and activates the word line. A method of writing data to a semiconductor memory cell that is coupled to a word line and single bit line is also provided.

Abstract: A method for designing a processor core is provided. Configuration registers are programmed by providing a cell configured at either one or zero for each bit of the configuration registers. Each configured cell is a latch with a data input and control signal inputs for receiving a direct resetting command and a direct setting command, and is configured at either one or zero by inhibiting either the direct resetting command or the direct setting command. Further, writing into the cells is permitted only in a test mode. Also provided is a method for designing and programming a processor core of the type having configuration registers. According to this method, a non-programmed processor core is designed by providing one vacant cell for each bit of the configuration registers. The vacant cell has the same abstract as both cells configured at one and cells configured at zero.

Abstract: The protection circuit includes a reference voltage source and at least one circuit which are connected together via a switch. A memory element is connected to the input of the circuit, downstream of the switch. The switch is temporarily opened by a control signal generated by a monostable circuit when detecting switching of power elements belonging to an electronic device embedding the protection circuit. When the switch is open, the memory element supplies the circuit with the reference voltage previously stored. In this way, switching of the power element that might cause noise on the reference voltage cannot disturb the circuit and thereby cannot cause a faulty operation of the latter.