Abstract: A driver circuit drives a power element connected to an inductive load. The driver circuit includes an output terminal, and a first current generator is connected between a voltage reference and the output terminal for providing a first charge current to a control terminal of the power element, which is connected to the output terminal. The driver circuit also includes a second current generator connected in parallel with the first current generator. The second current generator is connected between the voltage reference and the output terminal, and provides the control terminal with a second charge current dependent on a voltage present at the input terminal. The input terminal is connected to a conduction terminal of the power element.

Abstract: A generator includes an oscillator for producing a clock signal from N logic signals representing an N-bit control number, with N being an integer greater than 1. The oscillator has N+1 components. The N most significant components are each assigned a place value i ranging from 1 to N, and a least significant component provides the clock signal. At least one component with a place value i greater than 1 includes first and second arms. The first arm includes a cell and a first switch connected in series, and the second arm includes 1+21 cells and a second switch connected in series. Each cell includes an odd number of inverters.

Abstract: A generator includes an oscillator for producing a clock signal from an N-bit control number. The oscillator includes a first group of cells, with each cell including at least one series connected inverter. A first selection circuit selects a variable number of the cells as a function of the most significant bits of the control number. The oscillator also includes a second group of cells, with each cell including at least one series connected inverter. A second selection circuit selects one of the cells as a function of the least significant bits of the control number. The selected cells of the first and second groups of cells are series connected to form a chain of inverters.

Abstract: A method of controlling the movements of a multi-actuator electromechanical system having a matrix of locally interconnected analog cells associated therewith is provided. Each cell represents a hardware implementation of a model of fuzzy inference rules. The model includes a fuzzy circuit architecture which may be implemented in an integrated circuit with VLSI CMOS technology that generates and controls a reaction diffusion mechanism typical of auto-waves using a fuzzy neural network. The fuzzy neural network defines the functional relationships that may duplicate simultaneous reaction diffusion equations. The duplication of the simultaneous reaction diffusion equations is provided using two sets of fuzzy rules processing, in a linguistic manner, the state variables of the cells. An oscillatory type dynamic is imposed on each cell where two dynamic processes having different kinetic characteristics coexist.

Abstract: An integrated device in emitter-switching configuration is described. The device is integrated in a chip of semiconductor material of a first conductivity type which has a first surface and a second surface opposite to each other. The device comprises a first transistor having a base region, an emitter region and a collector region, a second transistor having a not drivable terminal for collecting charges which is connected with the emitter terminal of the first transistor, a quenching element of the first transistor which discharges current therefrom when the second transistor is turned off. The quenching element comprises at least one Zener diode made in polysilicon which is coupled with the base terminal of the first transistor and with the other not drivable terminal of the second transistor.

Abstract: Described herein is a read/write transducer for a hard disk drivewith dual actuation stage, comprising at least one hard disk and at least one suspension carrying the read/write transducer. The read/write transducer comprises a supporting body having a substantially parallelepipedal shape, a read/write head arranged on a front face of the supporting body, and a grating defined on one of the side faces of the supporting body during the process of manufacture of the read/write transducer. The grating enables measurement of the position of the read/write transducer with respect to the corresponding suspension in an optical way using a laser transmitter emitting and directing towards the grating a laser beam, and a laser receiver arranged to intercept the laser beam reflected by the grating and outputting a position signal on the basis of which it is possible to calculate, in a simple way, the position of the read/write transducer with respect to the corresponding suspension.

Abstract: The semiconductor device comprises a semiconductor substrate (SB) having locally at least one zone (ZL) terminating in the surface of the substrate and entirely bordered, along its lateral edges and its bottom, by an insulating material so as to be completely isolated from the rest of the substrate. The horizontal isolating layer may be a layer of constant thickness or a crenellated layer.

Abstract: The invention relates to a DRAM integration method that does away with the alignment margins inherent to the photoetching step of the upper electrode of the capacitance for inserting the bit line contact. The removal of the upper electrode is self-aligned on the lower electrode of the capacitance. This is accomplished by forming a difference in topography at the point where the opening of the upper electrode is to be made, and depositing a non-doped polysilicon layer on the upper electrode. An implantation of dopants is performed on this layer, and the part of the non-doped layer located in the lower part of the zone showing the difference in topography is selectively etched. The remainder of the polysilicon layer and the part of the upper electrode located in the lower layer are also etched.

Abstract: The method is intended for manufacturing a microintegrated structure, typically a microactuator for a hard-disk drive unit and includes the steps of: forming interconnection regions in a substrate of semiconductor material; forming a monocrystalline epitaxial region; forming lower sinker regions in the monocrystalline epitaxial region and in direct contact with the interconnection regions; forming insulating material regions on a structure portion of the monocrystalline epitaxial region; growing a pseudo-epitaxial region formed by a polycrystalline portion above the structure portion of the monocrystalline epitaxial region and elsewhere a monocrystalline portion; and forming upper sinker regions in the polycrystalline portion of the pseudo-epitaxial region and in direct contact with the lower sinker regions. In this way no PN junctions are present inside the polycrystalline portion of the pseudo-epitaxial region and the structure has a high breakdown voltage.

Abstract: There is provided an adjustable harmonic distortion detector that includes a clock signal source, means for the detection of a first period of evaluation, and means for the detection of a second period of evaluation. The detector has the characteristic that a first block memorizes a number equal to the clock pulses present in the first period of evaluation, a multiplier block performs a multiplication between the number stored in the first block and a multiplicative factor during the second period of evaluation, and a second block memorizes the outcome. The second block is adapted to generate an output signal when the outcome in the second block is equal to zero.

Abstract: A synthesizable, synchronous static RAM may include custom built memory cells and a semi-custom input/output/precharge section in bit slice form, a semi-custom built decoder connected to the bit slice, and a semi-custom built control clock generation section connected to the semi-custom built decoder and input/output section. The components may be arranged to provide high speed access, easy testability, and asynchronous initialization capabilities while reducing design time, and in a size that is significantly smaller than existing semi-custom or standard cell based memory designs.

Abstract: A regulating device for receiving a variable voltage and delivering a constant voltage includes a regulating element that includes a circuit for comparing the variable voltage with a reference voltage, a circuit for dividing the variable voltage by a factor, and a switching circuit for supplying the regulating element with a voltage equal either to the variable voltage or to the divided variable voltage. The switching circuit may be controlled by the comparison circuit in such a way that the regulating element is supplied with the variable voltage if a voltage condition is not satisfied and with the divided variable voltage if the voltage condition is satisfied.

Abstract: A control circuit for controlling current of batteries at the end of the charging phase, especially for lithium batteries, including an input/output circuit, placed between a battery charger and a battery, and an output stage, including two transistors, wherein the resistance of one of the two transistors is modulated to increase the value of the total resistance and to cause a lower turning off current of said output stage.

Abstract: A method of manufacturing DRAM cells in a substrate, including the steps of: depositing a first conductor in first openings in a first insulator partially exposing source/drain regions; opening a second insulator to partially expose the first openings contacting the source/drain regions, depositing a second conductor, then a third insulator, delimiting in the third insulator and second conductor bit lines of the memory cells, and forming lateral spacers on the sides of the bit lines; opening a fourth insulator to partially expose the first openings in contact with the drain/source regions of the transistors; depositing and etching a third conductor; conformally depositing a dielectric; and depositing a third conductor.

Abstract: The demodulating device for a chrominance signal includes an oscillator with a controlled frequency, and an adjuster for adjusting the oscillator frequency as a function of a charge voltage of a memory capacitor. The adjuster preferably includes a fine adjustment channel to output a first adjustment value that depends on the charge voltage of the memory capacitor, and a coarse adjustment channel to output a second adjustment value. The second adjustment value is modified when the charge voltage of the memory capacitor is not within a given range. The device is used, for example, in integrated SECAM decoders.

Abstract: A low-noise quadrature phase I-Q modulator having a pair of Gilbert cell input stages driven by a feed voltage line and receiving in input respective square wave command signals coming from a local oscillator. The modulator comprises a transistor block with transistors connected to each cell and destined to carry out a voltage-current conversion of a signal in radio frequency received from the block itself; such block further including a single degeneration resistance.

Abstract: A method for forming an aluminum contact through an insulating layer includes the formation of an opening. A barrier layer is formed, if necessary, over the insulating layer and in the opening. A thin refractory metal layer is then formed over the barrier layer, and aluminum deposited over the refractory metal layer. Proper selection of the refractory metal layer and aluminum deposition conditions allows the aluminum to flow into the contact and completely fill it. Preferably, the aluminum is deposited over the refractory metal layer without breaking vacuum.

Abstract: An infrared detector device having a PN junction formed by a first semiconductor material region doped with rare earth ions and by a second semiconductor material region of opposite doping type. The detector device comprises a waveguide formed by a projecting structure extending on a substrate, including a reflecting layer and laterally delimited by a protection and containment oxide region. At least one portion of the waveguide is formed by the PN junction and has an end fed with light to be detected. The detector device has electrodes disposed laterally to and on the waveguide to enable efficient gathering of charge carriers generated by photoconversion.

Abstract: Methods and an apparatus for storing information in a processing device with flexible security are disclosed. In one embodiment, an apparatus processes back-to-back write and read operations without stalling the processor. A cache memory subsystem buffers write operations between a central processing unit (CPU) and the cache memory subsystem. Included in the cache memory subsystem are a tag memory, a data memory and a store buffer. The store buffer is coupled to both the data memory and the tag memory. Additionally, the store buffer stores a write operation.

Abstract: The switch circuit receives a first supply voltage and a second supply voltage different from each other; a control input receiving a control signal that may be switched between the first supply voltage and ground; a driving inverter stage supplied by the second supply voltage and defining the output of the circuit; a feedback inverter stage supplied by the second supply voltage and including a top transistor and a bottom transistor defining an intermediate node and having respective control terminals. The control terminal of the top transistor is connected to the output node, the control terminal of the bottom transistor is connected to the control input, and the intermediate node is connected to the input of the driving inverter stage. An activation element helps switching of the intermediate node from the second supply voltage to ground; current limiting transistors are arranged in the inverter stages to limit the current flowing during switching and to reduce the consumption of the circuit.