Abstract: There is disclosed a field programmable gate array for use in an integrated processing system capable of testing other embedded circuit components in the integrated processing system. The field programmable gate array detects a trigger signal (such as a power reset) in the integrated processing system. In response to the trigger signal, the field programmable gate array receives first test program instructions from a first external source and executes the first test program instructions in order to test the other embedded circuit components in the integrated processing system. When testing of the other embedded circuit components is complete, the field programmable gate array loads its normal operating code and performs its normal functions.

Abstract: An electronic system, an integrated circuit and a method for display are disclosed. The electronic system contains a first device, a memory and a video/audio compression/decompression device such as a decoder/encoder. The electronic system is configured to allow the first device and the video/audio compression/decompression device to share the memory. The electronic system may be included in a computer in which case the memory is a main memory. Memory access is accomplished by one or more memory interfaces, direct coupling of the memory to a bus, or direct coupling of the first device and decoder/encoder to a bus. An arbiter selectively provides access for the first device and/or the decoder/encoder to the memory. The arbiter may be monolithically integrated into a memory interface. The decoder may be a video decoder configured to comply with the MPEG-2 standard. The memory may store predicted images obtained from a preceding image.

Abstract: A method of packaging a chip made in a semiconductor wafer. The method includes providing, on a first surface of the wafer, a conductive area extending beyond the periphery of the chip; adding a first thick plate including an electrically isolating material on the first surface; etching the conductive layer from a second surface of the wafer and depositing a conductive track extending from a contact of the second chip surface to the exposed surface of the conductive area; covering the second surface with a second thick plate forming a rigid cap; and etching the first plate above the conductive layer to deposit thereon a conductive material extending, in the form of a track, to the exposed surface of the first plate.

Abstract: A system and method regulates an alternator charging system and includes a memory for storing and regulating voltages used at specific temperatures for the specific alternator charging system requirements of an alternator. A circuit generates a digital signal indicative of both temperature of a battery supplied by the alternator charging system and the charging system voltage. A digital comparator receives the digital signal and compares the digital signal with the regulating voltage stored within the memory for the specific temperature that is indicative of the temperature of the battery supplied by the alternator charging system to generate a regulator control signal.

Abstract: The soft decisions associated with the quadrature digital signals received are calculated on the basis of at least one parametric law slaved to the minimum value of the rate of erroneous bits. The value is determined at the output of a Viterbi decoder in a microcontroller by varying the parameter of the law. The approach may be applied to applications including terrestrial digital broadcasting according to the DVB-T standard using OFDM modulation.

Abstract: An operational amplifier is provided that includes an inverting input channel, a non-inverting input channel, and an output stage. Each of the input channels controls at least one input transistor, and the output stage supplies an output voltage as a function of a potential difference at the input channels. Additionally, the operational amplifier includes at least one signal correction element in association with at least one of the input channels. The signal correction element is selectively put into circuit to selectively add an offset voltage correction signal to a signal that is supplied to the output stage in order to balance the characteristics of the two input channels. Also provided is a circuit for correcting the offset voltage of an operational amplifier.

Abstract: A capacitive high voltage generator comprising a first stage and a second stage respectively formed by a first basic block and a second basic block and a third basic block. Each basic block has a timing input, a first supply input, a second supply input and an output terminal and comprises: a buffer having a first terminal connected to the first supply input of the corresponding basic block, a second terminal connected to a ground terminal and an input terminal connected to the timing input of the corresponding basic block; a capacitor having a first terminal connected to an output terminal of the corresponding buffer and a second terminal connected, in a non-disconnectable way, to the output terminal of the corresponding basic block; a diode having a first terminal connected to the second supply input and a second terminal connected, in a non-disconnectable way, to the output terminal of the corresponding basic block.

Abstract: An amplifier includes an input stage with one or more input terminals for receiving a signal to be amplified, and an output terminal. An inverting gain stage includes an input terminal connected to the output terminal of the input stage, an output terminal for delivering an amplified signal, and a variable feedback resistor connected between the output terminal and input terminal thereof. The input stage is a transconductor stage biased by a current source. A transconductance thereof is set by a resistor of the current source so that the amplifier has a gain proportional to the product of the variable feedback resistor multiplied by the transconductance.

Abstract: A codifying and storing method for membership functions representing a membership degree of fuzzy variables defined within a universe of discourse which is discretized into a finite number of points is provided. The membership functions are quantized into a finite number of levels corresponding to a finite number of membership degrees and are stored by means of a characteristic value of each sub-set of values of fuzzy variables having for their image the same value of the membership degree corresponding to one of said levels. Also provided is a method for calculating the value of the membership degree of a fuzzy variable defined within a universe of discourse discretized into a finite number of points with reference to a membership function thereof, as well as to a circuit for calculating the membership degree of a fuzzy variable with reference to a membership function thereof.

Abstract: Presented is an EEPROM circuit comprising: a program array of a matrix of EEPROM cells arranged in columns and rows, a data array of a matrix of EEPROM cells arranged in columns and rows, the cells of the program and data array capable of being written, read, and erased; a reference voltage circuit coupled to the program array capable of producing voltages used to write to and erase data from the program array; a current generation circuit coupled to the program array for supplying current to the program array in operation. Advantageously according to the invention, the reference voltage circuit and the current generation circuit are additionally coupled to the data array. Moreover, the EEPROM circuit further comprises means for selectively connecting at least one of the rows of the program array to one of the rows of the data array, and for selectively connecting at least one of the columns of the program array to one of the columns of the data array.

Abstract: Lighting flicker in the output of a video imaging device is detected. The video imaging device has a main picture area divided into pixels for producing successive images at a frame rate. A series of signals are produced from at least one additional picture area adjacent the main picture area, with the additional picture area having a size substantially larger than a pixel. Each of the signals is a function of light incident on the additional picture area in a time period substantially shorter than that of the frame rate. A predetermined number of the signals are accumulated to form a series of compound samples, and the compound samples are filtered to detect components indicating the lighting flicker. The filtering is performed using a bandpass filter tuned to the nominal flicker frequency. The compound samples are formed at a sample rate which is a multiple of the nominal flicker frequency, and the filtering is performed by taking the fundamental output component of a radix-N butterfly.

Abstract: Described herein is a nonvolatile memory comprising a memory array organized according to global word lines and local word lines; a global row decoder; a local row decoder; a first supply stage for supplying the global row decoder; and a second supply stage for supplying the local row decoder; and a third supply stage for biasing the drain and source terminals of the memory cells of the memory array. Each of the supply stages comprises a respective resistive divider formed by a plurality of series-connected resistors, and a plurality of pass-gate CMOS switches each connected in parallel to a respective resistor. The nonvolatile memory further comprises a control circuit for controlling the pass-gate CMOS switches of the supply stages, and a switching circuit for selectively connecting the supply input of the control circuit to the output of the second supply stage during reading and programming of the memory, and to the output of the third supply stage during erasing of the memory.

Abstract: A VLSI architecture adapted to be implemented in the form of a reusable IP cell and including a motion estimation engine, configured to process a cost function and identify a motion vector which minimizes the cost function, an internal memory configured to store the sets of initial candidate vectors for the blocks of a reference frame, first and second controllers to manage the motion vectors and manage an external frame memory, a reference synchronizer to align, at the input to the estimation engine, the data relevant to the reference blocks with the data relevant to candidate blocks coming from the second controller, and a control unit for timing the units included in the architecture and the external interfacing of the architecture itself.

Abstract: The buffer has an output stage formed by two complementary MOS transistors connected so as to operate in phase opposition between the supply terminals and two driver stages having the input in common. Each driver stage has a first branch comprising a current-generator connected between the gate electrode of the transistor to be driven and a supply terminal and an electronic switch controlled by the input and connected between the same gate electrode and the other supply terminal, and a second branch which comprises, connected in series, a transistor connected as a diode and an electronic switch controlled by the output, and is arranged between the gate electrode of the transistor to be driven and a respective supply terminal. The buffer can control a load with a constant switching current, is simple in structure, and occupies a small area.

Abstract: In a method for the display of text on a screen of a television receiver, the digital data representing a received text are decoded to give, first, a list of characters to be displayed including at least one character and a color palette including at least one color, and second, a matrix of pixels associated with the list of characters to be displayed. Each element of the matrix of pixels defines the color of a corresponding point of the screen. To obtain a visual effect on at least one point of the screen, at least one color of the color palette is modified. The display method may be implemented in a television receiver.

Abstract: A distance sensor has a capacitive element in turn having a first capacitor plate which is positioned facing a second capacitor plate whose distance is to be measured. In the case of fingerprinting, the second capacitor plate is defined directly by the skin surface of the finger being printed. The sensor comprises an inverting amplifier, between the input and output of which the capacitive element is connected to form a negative feedback branch. By supplying an electric charge step to the input of the inverting amplifier, a voltage step directly proportional to the distance being measured is obtained at the output.

Abstract: A circuit is provided for reducing losses of the start of a new message caused by the microcontroller of a slave apparatus being unavailable. The circuit generates an interruption signal when the slave apparatus has received and acknowledged a start of a new message but the microcontroller is unavailable because it is processing a preceding message or an application of the slave apparatus.

Abstract: An electronic device, such as an opto-electronic device and an integrated semiconductor memory device, includes at least one integrated memory point structure including a quantum well semiconductor area buried in the substrate of the structure and disposed under the insulated gate of a transistor. A biasing voltage source is adapted to bias the structure to enable charging or discharging of charges in the quantum well or outside the quantum well.

Abstract: A circuit for reading a non-volatile memory cell has an output terminal for providing an output current, and a control terminal for receiving a voltage for controlling the output current. The reading circuit includes a feedback circuit which can be connected electrically to the output terminal and to the control terminal to generate the control voltage from a reference signal and from the output current. The feedback circuit also includes a current-amplification circuit having a first terminal for receiving a current-error signal derived from the reference signal and from the output current, and a second terminal for supplying an amplified current.

Abstract: The system can be used for the automatic analysis of images (I), comprising a matrix of spots, such as images of DNA microarrays after hybridisation. The system can be associated—and preferably integrated in a single monolithic component implementing VLSI CMOS technology—to a sensor (10) for acquiring said images (I). The system comprises a circuit (20) for processing the signals corresponding to the images (I), configured according to a cellular neural network (CNN) architecture for the parallel analogue processing of signals.