Abstract: A set of sampling capacitors weighted according to a binary code is charged through a first capacitive unit, whose capacitance is equal to the sum of the capacitances of the set, at a voltage Vcm−Vin/2. The conversion is carried out by an SAR process by a comparator and a logic unit which operates the switches associated with the capacitors. The final position of the switches is loaded into a register which supplies the digital output signal. To prevent any disturbances in the power supply and reference potential sources from affecting the accuracy of the conversion, two further capacitive units are provided, with the same capacitance as the first capacitive unit. These make it possible to prevent all the disturbances at the input of the comparator in common mode and therefore without any effect on the output.

Abstract: A circuit for generating an output voltage proportional to temperature with a required gradient, the circuit including a first stage arranged to generate a first voltage which is proportional to temperature with a predetermined gradient, the first stage including first and second bipolar transistors with different emitter areas having their emitters connected together and their bases connected across a bridge resistive element, wherein the collectors of the transistors are connected to an internal supply line via respective matched resistive elements as the voltage across the bridge resistive element is proportional to temperature; a differential amplifier having its input connected respectively to the collectors, and its output connected to stabilisation circuitry connected between first and second power supply rails and an internal supply line which cooperates with the differential amplifier to maintain a stable voltage on the internal supply line despite variations between the first and second power supply

Abstract: A device and associated methods for the storage and retrieval of data elements in a buffer circuit include each data element being transmitted to the buffer circuit through a transmission bus and a bus interface. A data element is stored in a memory when a first register is not empty. Additionally, when the first register is not empty, a data element is also stored in an additional register directly accessible by a decoding interface. The time of access to the data elements in the buffer circuit may be reduced.

Abstract: A communications system, a digital modem and method are provided for reducing non-linear distortion generated by a transmitter which adversely affects a receiver attempting to demodulate received data. More specifically, the digital modem includes a controller that controls a receiver and a transmitter. The receiver is operable to receive a plurality of receiver tones, and the transmitter is operable to generate a plurality of transmitter tones whose intermodulation products (transmitter non-linear distortion) conflict with the plurality of receiver tones. The transmitter is also operable to shift the plurality of transmitter tones by a predetermined distance to move the conflicting intermodulation products off the plurality of receiver tones.

Abstract: A driver circuit drives a power element connected to an inductive load. The driver circuit includes an input terminal coupled to a control terminal of the power element through a trigger block, and a voltage regulator block having a circuit node coupled to a first supply voltage reference, as well as to a second supply voltage reference through a capacitor. A voltage comparator stage includes an operational amplifier having an inverting input connected to the circuit node and a non-inverting input is connected directly to a terminal of the power element, such as to the emitter terminal thereof. The operational amplifier also includes an output connected to the control terminal of the power element.

Abstract: A sensor having an array of photo sensitive elements for acquiring images of the passenger compartment in a motor vehicle and a circuit for processing the signals corresponding to the images generated by said photo sensitive elements. The processing circuit is configured according to a cellular neural network processing architecture of the image signals and can generate an output signal indicating the decision on whether to deploy an airbag to which the sensor is associated or to control the explosion of the airbag. Preferably, the photo sensitive array and the processing circuit are comprised on a single integrated component, preferably implementing CMOS technology.

Abstract: An electromagnetic transponder including an oscillating circuit adapted to extracting from a radiating field a high-frequency amplitude-modulated signal, circuitry for extracting from said high-frequency signal an approximately D.C. supply voltage, a demodulator of data carried by the high-frequency signal, and circuitry for separately regulating the supply voltage and a useful voltage carrying the data.

Abstract: A method is for driving an output buffer for outputting a datum of a certain voltage level with a certain slew-rate as a function of an input datum and a first enabling signal. The first enabling signal commands the buffer to a normal functioning state or to a high impedance state. The output buffer has an output stage controlled at least by a pull-up driving circuit and a pull-down driving circuit, and an enabling circuit input with the input datum and a second enabling signal and generating control signals. The control signals may be in phase or in phase opposition depending on whether the second enabling signal is active or disabled, and they are input into the respective driving circuits.

Abstract: A process that includes forming a metal layer on top of a wafer of semiconductor material; forming a mask having an appropriate geometry; defining the metal layer to form conductive lines in the metal layer according to the geometry of the mask; forming, on side walls of the mask a polymeric structure; selectively removing the mask; depositing, on the polymeric structure and on the conductive lines, an insulating material. The polymeric structure, made of an inorganic polymer, forms a “supporting bridge” for the insulating material, preventing the latter from depositing in the gaps between the conductive lines. In these conditions, the gap between two adjacent conductive lines is occupied only by air, which has a very low dielectric constant. This results in a reduced capacitive coupling between the lines themselves.

Abstract: A method of programming a plurality of memory cells are connected in parallel between first and second supply references and having their gate terminals connected together and, through row decoding means, also connected to an output terminal of an operational amplifier that is adapted to generate a word voltage signal, the first voltage reference being provided by a charge pump circuit. The programming method uses a program loop that includes the cells to be programmed and the operational amplifier, the charge pump circuit thus outputting a voltage ramp whose slope is a function of the cell demand. A programming circuit adapted to implement the method is also provided.

Abstract: A smart card reader includes a housing for receiving a smart card, a microprocessor, and a connector for connecting the microprocessor to the received smart card for establishing communications therebetween. A voltage source provides a power supply voltage to the microprocessor based upon the smart card being received in the housing. The smart card reader further includes a first switch interposed between the voltage source and a power supply terminal of the microprocessor. The first switch is closed when the received smart card is at an end of travel in the housing so that the power supply voltage is provided to the microprocessor, and is opened when the received smart card is no longer at the end of travel in the housing so that the power supply voltage is not provided to the microprocessor.

Abstract: A memory chip which uses a multi-pin port as a JTAG port includes a JTAG controller, at least one internal block and a configuration unit which selectively configures four pins of the multi-pin port to communicate JTAG data to the JTAG controller or to communicate non-JTAG data to the at least one internal block. The configuration unit can be generally permanent or it can be modifiable. For example, the modifiable configuration unit can be a volatile memory (VM) configuration unit or a product term output of a programmable logic device (PLD).

Abstract: An amplifier having an input; an output supplying an output signal, and a feedback network connected between the input and the output, and a distortion detection circuit. The feedback network includes a first and a second feedback element arranged in series and forming an intermediate node supplying an intermediate signal in phase with the output signal in absence of distortion, and in phase-opposition with the output signal in presence of distortion. The distortion detection circuit includes a phase-comparating circuit which detects the phase of the output signal and of the intermediate signal, and generates a distortion-indicative signal, when the intermediate signal is in phase opposition with respect to the output signal.

Abstract: A voltage boosting device for speeding power-up of multilevel nonvolatile memories, including a voltage regulator and a charge pump and having an output terminal; the voltage regulator having a regulation terminal connected to the output terminal, and an output supplying a control voltage; the read charge pump having an output connected to the output terminal and supplying a read voltage. The device further includes an enable circuit connected to the output and having a pump enable output connected to a charge pump enable terminal and supplying a pump enable signal. The pump enable signal is set at a first logic level so as to activate the charge pump when the read voltage is lower than a nominal value. In addition, the device generates a power-up sync signal which activates a read operation when the read voltage reaches its nominal value and a chip enable signal is set at an active value.

Abstract: The invention relates to a digital timer (20) comprising a binary counter (21) driven by a counting clock signal (Hc), the counter (21) presenting a stabilization time after each counting pulse, and means for delivering a detection signal (DS2) with a predetermined value when a counting order (N) is reached by the counter. According to the invention, the timer comprises wired logic means (22) arranged for detecting, at the output of the counter, a counting value (N−1) which is immediately before the counting order (N) in relation to the counting direction, and delivering an intermediate signal (DS1) with a predetermined value, as well means (24) for sampling the intermediate signal (DS1) at a moment when the counter receives the next counting pulse.

Abstract: The invention provides a method and apparatus for the modulation of more than one channel of audio in a digital amplification system. In the preferred embodiment of the invention, pulse width modulator outputs are staggered in time such that at idle only one channel switches states at a time. This is done to provide an even draw from the power supply, assuming that the same supply is used for the multiple channels. For example, in a two channel system, the idle state of the pulse width modulator for the first channel is 90 degrees out of phase with the pulse width modulator output of the second channel.

Abstract: An injection-molding mold having two parts adapted to take up between them the periphery of a substrate and one of which defines a molding cavity connected to means for feeding a coating material for encapsulating a row of spaced integrated circuit chips carried by a mounting face of said substrate and placed in said cavity, characterized in that the part (10) with cavities (14) includes a slot (17) for injecting the coating material into said cavity above the mounting face (2) of the substrate, recessed into its face (12) bearing on the substrate (1) along said row of chips and extending approximately the whole length of that row of chips.

Abstract: An electronic circuit is for the gradual start-up of electric loads, particularly halogen lamps. The circuit may include a power device having an output terminal connected to the electric load and having at least one control terminal receiving a predetermined driving current value. The circuit may further include a comparator having a first input terminal coupled to the power device output and a second input terminal kept at a reference potential. The comparator output may be connected to a controlled switch inserted upstream of the control terminal to control the opening of the switch and adjust the start-up phase of the power device according to the value of the reference potential.

Abstract: A modulation/demodulation device capable of operating with several types of modulation using different carrier frequencies may include a modulator which modulates at least one signal by a signal of a predetermined duration and representative of a binary information supplied by a microprocessor. The device may also include a demodulator which demodulates the modulated signals arriving from a remote site. This may be done by determining the type of modulation of the received signals and their carrier frequency (or frequencies), supplying signals from an analysis of the signals received according to the determined type of modulation, and detecting the signals of determined duration representative of binary information to make them accessible to the microprocessor.

Abstract: Semiconductor power device including a semiconductor layer of a first type of conductivity, wherein a body region of a second type of conductivity including source regions of the first type of conductivity is formed, a gate oxide layer superimposed to the semiconductor layer with an opening over the body region, polysilicon regions superimposed to the gate oxide layer, and regions of a first insulating material superimposed to the polysilicon regions. The device includes regions of a second insulating material situated on a side of both the polysilicon regions and the regions of a first insulating material and over zones of the gate oxide layer situated near the opening on the body region, oxide regions interposed between the polysilicon regions and the regions of a second insulating material, oxide spacers superimposed to the regions of a second insulating material.