Abstract: A method for communicating between a transmitting unit and a receiving unit. A messages formed by elementary messages is transmitted from the transmitting unit to the receiving unit, and at least one reception bit is transmitted from the receiving unit to the transmitting unit. The reception bit (or bits) allows the transmitting unit to determine the elementary message that is to be transmitted next. In a preferred method, at least two reception bits are transmitted from the receiving unit and the values of the reception bits indicate the elementary message that is to be transmitted next by the transmitting unit. The present invention also provides a receiving device for receiving messages from a transmitting device. The receiving device includes an interface for receiving a transmitted message from the transmitting device, means for analyzing a received elementary message to determine if it was properly received, and a transmitter for transmitting at least one reception bit to the transmitting device.

Abstract: An initial single-crystal substrate 1 having, locally and on the surface, at least one discontinuity in the single-crystal lattice is formed. The initial substrate is recessed at the discontinuity. The single-crystal lattice is amorphized around the periphery ofthe recess. A layer ofamorphous material having the same chemical composition as that ofthe initial substrate is deposited on the structure obtained. The structure obtained is thermally annealed in order to recrystallize the amorphous material so as to be continuous with the single-crystal lattice ofthe initial substrate.

Abstract: Method for manufacturing an SOI wafer. On a monocrystalline silicon wafer, forming protective regions having the shape of an overturned U, made of an oxidation resistant material, the protective regions covering first wafer portions. Forming deep trenches in the wafer which extend between, and laterally delimit the first wafer portions, completely oxidizing the first wafer portions except their upper areas which are covered by the protective regions, to form at least one continuous region of covered oxide overlaid by the non-oxidized upper portions. Removing the protective regions, and epitaxially growing a crystalline semiconductor material layer from the non-oxidized upper portions.

Abstract: A voltage regulating device includes a comparison circuit for comparing a voltage proportional to an output voltage to a fixed reference voltage. The fixed reference voltage is received on a first input and the voltage proportional to an output voltage is received on a second input. The voltage regulating device further includes a variable resistance-forming circuit controlled by the output of the comparison circuit and disposed so that the output voltage remains substantially constant. The voltage regulating device may be supplied with a variable input voltage. The voltage regulating device further includes a second comparison circuit so that the output voltage remains substantially constant if the input voltage is greater than a threshold, and substantially equal to the input voltage if the input voltage is less than the threshold.

Abstract: A method and a bit counting device (100) count bits set to one in a data word of arbitrary size. The bit counting device (100) includes a first data register (110) for storing a data word, an offset register (112) for storing an offset value, a second data register (120), and a one-cycle shifter (114), electrically connected to the first data register (110), to the second data register (120), and to the offset register (112), for shifting the data word by a value stored in the offset register (112) and storing the shifted data word in the second data register (120).

Abstract: A method and a computing system compute an incremental checksum corresponding to a data packet. The incremental checksum is computed within one processor cycle of a processor. A first register (102) stores first checksum information corresponding to a data packet. A second register (104) stores second checksum information corresponding to old information being deleted from the data packet. A third register (106) stores third checksum information corresponding to new information being added to the data packet. An incremental checksum circuit (100), electrically connected to the first register (102), to the second register (104), and to the third register (106), provides resulting checksum information corresponding to the data packet after deleting the old information from the data packet and adding the new information to the data packet. The resulting checksum information is selectively stored in the first register (102).

Abstract: The present invention relates a current zero crossing detecting circuit including a PWM driving half bridge circuit, which generates an output signal (OUT) and a signal synchronous with the high impedance condition of said PWM driving half bridge circuit. Said inventive circuit has the characteristic of comprising detecting means (DFLIP, COMP) synchronous with said signal synchronous with the high impedance condition of said PWM driving half bridge circuit and said output signal (OUT), and said detecting means generating a direction signal (DIR_COR) showing the current direction flowing in said pulse width modulation circuit.

Abstract: A method for maximizing buffer usage in a disk drive system. Control circuitry within the disk drive system tansfers the defective sector list for the disk to a buffer, and places the list in a reserved list area. The size of the defective sector list is then determined and the reserved list area is reduced to a size equal to the size of the defective sector list plus some spare room. If the newly sized reserved list area is not at one end of the buffer, it is then moved to one end of the buffer to leave the remainder of the buffer as a contiguous and expanded reserved user area for use data. The expanded reserved user area reduces the time of read or write operations in a disk drive.

Abstract: A method of cutting a wafer of a semiconductor material, including breaking the wafer along cutting paths using a knife hitting a sheet supporting the wafer in a frame. The method includes using knives of different lengths according to the wafer region in which the cutting path is located using a tool block including apparatus for receiving at least two knives of different lengths and for rotating step-by-step around an axis to change the knife that is active in the wafer cutting.

Abstract: An OTP memory cell in CMOS technology, including a capacitor associated in series with an unbalanced programming transistor, the drain of which is made of a region deeper and less doped than the source.

Abstract: A ROM including an array, each cell of which is accessible by means of a column address and of a row address, includes a parity memory for storing the expected parity of each row and of each column, an electrically programmable one-time programmable address memory, a testing circuit for, during a test phase, calculating the parity of each row and of each column, comparing the calculated and expected parities for each row and each column, and in case they are not equal, marking the row or column in the address memory, and a correction circuit for, in normal mode, inverting the value read from the array cell, having its row and column marked in the address memory.

Abstract: A CMOS technology voltage booster having plurality of charge-pump stages cascade connected together and driven by a plurality of phases, each stage having a terminating input node and a terminating output node, with at least one transistor connected therebetween that has its control terminal connected to an internal circuit node of the same stage and applied one of the phases. This voltage booster further includes a pair of additional circuit elements for transferring, onto the internal node, a potential exceeding the voltage at the input node by at least one threshold. A first of the additional elements is essentially a MOS transistor having its control terminal connected to the control terminal of that transistor that is connected between the input and the output of the stage, while the second additional element is an auxiliary capacitor having one end connected directly to the first additional element and connected to the internal node through a transistor.

Abstract: The ROM memory cell, not decodable by visual inspection comprises a substrate of semiconductor material having a first conductivity type, in particular P−. A first MOS device having a first threshold voltage is formed in a first portion of the substrate, and a MOS device having a second threshold voltage, greater than the first threshold voltage, is formed in a second portion of the substrate adjacent to the first portion. The second MOS device is a diode reverse biased during a reading phase of the ROM memory cell and comprises a source region having the first conductivity type and a drain region having a second conductivity type. The source region has a level of doping higher than that of the substrate.

Abstract: An integrated circuit electrically is supplied with a voltage and includes an output MOS transistor having a gate driven by an output of a logic circuit and a circuit for biasing the gate of the output MOS transistor. The circuit for biasing the gate is provided for lowering a gate-source bias voltage of the output MOS transistor in a conductive state in relation to the gate-source bias voltage that would otherwise be provided by the output of the logic circuit. The present invention is particularly applicable to output stages for I2C buses.

Abstract: A manufacturing method having the steps of: depositing an upper layer of polycrystalline silicon; defining the upper layer, obtaining LV gate regions of low voltage transistors and undefined portions; forming LV source and drain regions laterally to the LV gate regions; forming a silicide layer on the LV source and drain regions, on the LV gate regions, and on the undefined portions; defining salicided HV gate regions of high voltage transistors; and forming HV source and drain regions not directly overlaid by silicide portions.

Abstract: The present invention is a temperature sensor which is based on the actual temperature coefficients of a device in the circuit, rather than a predetermined threshold voltage that varies across different devices. This temperature sensor includes a circuit which determines the temperature of a device. More particularly, CMOS circuit is provided which uses a current source to generate charge and discharge voltages applied to a capacitor. These voltages are dependent on the temperature coefficient of a resistor in the current source. The charge and discharge times are then used to determine a frequency which is dependent on the temperature coefficient of the resistor. Thus, the temperature is sensed based on the output frequency of the circuit. Additionally, the present invention includes a mechanism which allows the temperature sensor to be activated or deactivated as needed.

Abstract: Described in the disclosure is a method for fabricating high-capacitance capacitive elements that are integrated in a semiconductor substrate. First a dielectric layer is formed over the surface of the substrate and a metal layer is deposited thereon. The metal layer is patterned and etched to form lower plates of the capacitive elements, as well as to form interconnection pads. Then, an intermediate dielectric layer is deposited on the lower plates and interconnection pads, and over the entire exposed surface of the substrate. Following that, a sacrificial conductive layer is deposited onto the intermediate dielectric layer, and the upper plates of the capacitive elements are formed out of the sacrificial conductive layer. Then, an upper dielectric layer is formed over the entire semiconductor, and openings are formed in this layer for the upper plates and the interconnection pads.

Abstract: A serial resonant circuit, formed by EL panel (CEL) and coil (L1), is connected to a push-pull driver through a positive feedback path to form an oscillator circuit. The EL panel is driven by a sinusoidal driving signal to emit light. The voltage level of the EL panel driving signal is adjusted corresponding to the change in the capacitance of the EL panel so that the luminous brightness of the EL panel can be maintained on a constant level.

Abstract: A field-effect transistor and a method for its fabrication is described. The transistor includes a monocrystalline semiconductor channel region overlying and epitaxially continuous with a body region of a semiconductor substrate. First and second semiconductor source/drain regions laterally adjoin opposite sides of the channel region and are electrically isolated from the body region by an underlying first dielectric layer. The source/drain regions include both polycrystalline and monocrystalline semiconductor material. A conductive gate electrode is formed over a second dielectric layer overlying the channel region. The transistor is formed by patterning the first dielectric layer to selectively cover a portion of the substrate and leave an exposed portion of the substrate.

Abstract: A process for forming floating gate non-volatile memory cells in a cell matrix with associated control circuitry comprising both N-channel and P-channel MOS transistors is provided. The process includes forming active areas in a substrate for the cell matrix and the associated control circuitry. A first thin oxide layer and a first polysilicon layer are deposited on the active areas to produce floating gate regions of the memory cells, and a second dielectric layer is deposited on the active areas. A second polysilicon layer is then deposited on the active areas. A masking and etching step is performed for exposing the substrate for the associated control circuitry followed by the deposition of a third polysilicon layer. The third polysilicon layer is defined to produce the gate regions of the transistors for the associated control circuitry while the third polysilicon layer is removed from the cell matrix.