Abstract: An integrated circuit includes an array of memory cells that are selected by rows and read by columns. The columns are first precharged by an internal signal to then read the memory cells. The read is responsive to an edge of a clock signal and the read is of an unknown delay. A multiplexer output provides the internal signal. The multiplexer includes a plurality of inputs electrically connected to delay lines of different delay sizes that receive the edge of the clock signal. A multiplexer control circuit selects a delay line to provide the internal signal as soon as possible after the unknown delay.

Abstract: A process for fabricating a metal-metal capacitor within an integrated circuit comprises the steps of: producing a first metal electrode, a second metal electrode, and a dielectric layer on top of a lower insulating layer; and depositing an upper insulating layer on top of the two metal electrodes and the dielectric layer. The integrated circuit comprises the insulating layer, a first metal layer which is on top of the lower insulating layer, and the upper insulating layer which is on top of the first metal layer. The capacitor comprises the first metal electrode, the second metal electrode, and the dielectric layer wherein each of the two metal electrodes is in contact with one side of the dielectric layer. The electrodes and the dielectric layer lie between the lower insulating layer, which supports a level of metallization (M1), and the upper insulating layer which covers this level of metallization.

Abstract: An integrated device comprises at least one circuit element and a plurality of trimming elements which can be connected selectively to the at least one circuit element in order to achieve a predetermined tolerance of a characteristic parameter of the at least one circuit element; the integrated device includes a plurality of electronic switches, each of which can be switched between a first state and a second state in which it activates and deactivates a corresponding one of the trimming elements, respectively, and a memory for storing an indication of the states of the electronic switches and for operating each electronic switch in the first state or in the second state according to the indication stored.

Abstract: A master-slave D type flip-flop circuit includes a power consumption masking circuit including a reference stage in parallel with a master and a slave stage of the flip-flop circuit. This structure advantageously provides a switching of the flip-flop circuit on each of the leading and trailing edges of the clock signal for the sequencing of the flip-flop circuit.

Abstract: The invention relates to an elementary standard structure for the determining of the RF characteristics of an RF integrated circuit probe, comprising at least two contact pads deposited on a silicon substrate by means of an electrically insulating layer, at least one standard load that is measurable from the contact pads and a conductive screen buried beneath the insulating layer. The invention relates also to a standard circuit comprising a plurality of elementary standard structures arranged so as to present contact pads corresponding by their location to RF connection pads of the integrated circuit to be tested.

Abstract: Acoustic emission samples for a chemical mechanical polishing process are acquired and analyzed using a Fourier transform to detect wafer vibrations characteristic of scratching. When excess noise levels are detected at frequencies or within frequency bands being monitored, the polishing process is halted and an alarm is generated for the operator. Such in-situ detection minimizes damage to the wafer being polished and limits the damage to a single wafer rather than a run of wafers. Polish endpoint detection may be integrated within the scratch detection mechanism.

Abstract: An integrated circuit includes a first and second memory, with the first memory being configurable between a first data format and a second data format. An external address bus is connected to the second memory, and an internal bus is connected to the first memory. A rerouting circuit is connected between the external address bus and the internal bus. The rerouting circuit forms one of two connections between the external address bus and the internal bus dependent upon the configuration of the first memory.

Abstract: A voltage generator formed of a charge circuit and a discharge circuit having a common programmable voltage divider with variable resistance; the programmable voltage divider including a plurality of resistors arranged in series and selectively connectable to define alternatively a step-wise increasing program voltage and a fixed verify voltage. The charge circuit formed of a voltage regulator supplying at the output the precise voltage value determined by the programmable voltage divider, and the discharge circuit intervening when the output voltage must be switched in a controlled manner from a higher value to a lower value.

Abstract: A method for the electrical and/or mechanical interconnection of components of a microelectronic system includes at least one first component and at least one second component to be connected, and at least one local Joule-effect micro-heater is incorporated in one of the first and second components at a respective soldering point therebetween. The method includes supplying electrical energy to the micro-heater to utilize the heat produced therefrom by the Joule effect to solder the first and second components at the respective soldering point.

Abstract: In capacitive sensor circuits where physical contact is required and excess pressure may be inadvertently applied to the sensor surface, aluminum is not sufficiently hard to provide “scratch” protection and may delaminate, causing circuit failure, even if passivation integrity remains intact. Because hard passivation layers alone provide insufficient scratch resistance, at least the capacitive electrodes and preferably all metallization levels within the sensor circuit in the region of the capacitive electrodes between the surface and the active regions of the substrate are formed of a conductive material having a hardness greater than that of aluminum. The selected conductive material preferably has a hardness which is at least as great as the lowest hardness for any interlevel dielectric or passivation material employed.

Abstract: The operation Y0=(X*J0) mod 2Bt is implemented directly within a coprocessor to eliminate the need for, a register of Bt=m*k bits within the coprocessor. This eliminated register enables the storage of a data element during the computation of Y0. The operation S=A*B mod 2m*k is implemented with a circuit including at least three registers and a multiplication circuit. One of the registers simultaneously stores S and an intermediate result. To improve the method, a second multiplication circuit and registers of variable sizes are used.

Abstract: An output buffer, particularly for non-volatile memories, includes a push-pull output stage, a first data latch circuit receiving as an input data from an external data bus which connects at least one memory to the first data latch circuit, first and second activation paths for the activation of the push-pull stage, first and second circuits for enabling the push-pull stage, first and second circuits for disabling the push-pull stage, and second and third data latch circuits connected to the push-pull stage. More specifically, the first and second activation paths may be connected to the first data latch circuit. Furthermore, the first and second circuits for enabling the push-pull stage may be connected between the first data latch circuit and the push-pull stage.

Abstract: A converter that is directly connectable to an AC power source (e.g., the mains) includes a rectifier stage for rectifying a network voltage, a power factor correction pre-regulating circuit supplied with the rectified network voltage for producing a DC voltage of a predetermined nominal value on an output node, and a DC-DC converter. The DC-DC converter may be supplied on an input node thereof with the DC voltage of the predetermined nominal value for producing a regulated DC voltage on an output node thereof. The DC-DC converter may use a clock whose frequency is selected between at least one low and one high value by a selection signal. Furthermore, the converter may also include a stand-by circuit for producing the selection signal based upon the current delivered to the load.

Abstract: A BPSK encoder is provided with a first circuit which processes a carrier signal and a binary signal to be encoded, and produces an output binary signal having synchronous phase shifts representing a change in the value of the signal to be encoded. Also, the first circuit is provided with a sampling signal from a second circuit. The second circuit includes a delay circuit to deliver a shifted carrier signal that is smaller than the half-period of the carrier signal, and a logic gate for the logic combination of the carrier signal and the shifted carrier signal. The logic gate also delivers a binary sampling signal having at least two leading or trailing edges at each period of the carrier signal.

Abstract: It is shown a low noise amplifier comprising a first circuit block suitable for converting a first amplifier input voltage signal into current, a second circuit block adapted to divide the current coming from said first block, said second block being controlled by a second voltage signal, said first and second blocks conferring a variable voltage gain to the amplifier. The amplifier comprises at least one first and at least one second resistors and a feedback network, said at least one first resistor connected with one first output terminal of said second block and with a supply voltage, and said at least one second resistor being connected between said at least one first and at least one second output terminals of said second block, and said feedback network being coupled with said at least one first terminal and with said first circuit block, and said at least one second terminal being coupled with at least one output terminal of said low noise amplifier. (FIG. 3).

Abstract: An impedance control circuit controls the impedance of an integrated output driving stage. The integrated output driving stage includes at least one enabling/disabling transistor and at least one driving transistor. The impedance control circuit includes a variable impedance circuit having an impedance that varies with the temperature in correlation with the impedance of the output driving stage. A control circuit is connected to the variable impedance circuit for generating at least one enabling/disabling signal for the at least one enabling/disabling transistor based upon a control signal correlated to the impedance of the variable impedance circuit. The impedance control circuit also includes a current generating circuit for applying to the variable impedance circuit a current which remains substantially stable as the temperature varies.

Abstract: A method for storing pages of a teletext service, with at least one page being received by a storage circuit of a television receiver, is provided. The storage circuit includes a data memory for storing the at least one received page. The method includes extracting a reference number from the at least one received page, checking whether the at least one received page is a requested page, and evaluating contents of the data memory to decide whether the at least one received page is to be stored as a function of free space in the data memory and an importance of the at least one received page. The method also includes storing the at least one received page if it is decided that the at least one received page is to be stored.

Abstract: In order to estimate power consumption, over a given time interval, of digital circuits described at the level of functional elements provided with input/output terminals associated additional elements are emulated at the hardware level. The said additional emulated elements are able to detect, during said time interval, at least one signal indicative of the behavior of the functional element associated during hardware emulation of the circuit. Preferably the number of transitions performed during the aforesaid time interval of the associated functional element is recorded, as well as the fraction of time in which the state of said functional element is stable. The value of said signals is acquired to perform an estimation of the power consumption of the functional element during the aforesaid time interval.

Abstract: A method is for forming a plastic protective package for an electronic device integrated on a semiconductor and comprising an electronic circuit to be encapsulated in the protective package. The electronic device may be at least partially activated from outside of the protective package. The method may include providing a mold having a half-mold with an insert abutting towards the inside of the mold and an end having an element that can be elastically deformed to abut in pressing contact against at least one portion of the integrated circuit. The method may also include injecting a resin into the mold so that the protective package has a hole by the at least one portion of the electronic circuit.

Abstract: A device for detecting load impedance having an analog circuit portion for detecting the impedance value of a load, and a digital circuit portion adapted to provide load impedance type information. The analog circuit portion having two power MOS transistors connected in series to each other and between a supply voltage and the ground, and a pair of mirror MOS transistors common-connected with their respective gate terminals to the gate terminals of the power MOS transistors. The digital circuit portion includes a first comparitor to determine whether the output current of an audio amplifier is higher or lower than a threshold value and a second comparitor to determine whether the output voltage of the amplifier is higher than a threshold voltage, a memory to store output signals of the first and second comparitors, and a logic circuit arranged in cascade with the memory to output a load-type indication signal.