Abstract: A method for detecting a zero-cross event of an induced back electromotive force (BEMF) or of a nullification instant of a periodic current in a PWM driven winding, by circuits generating an analog signal representative of the induced BEMF or of the nullification instant of the periodic current, comparing the analog signal with zero and producing a first logic signal, generating a PWM driving signal, and storing a time between two consecutive zero-cross events, is provided. The method may include storing a time between a last two zero-cross events and synchronizing the PWM driving signal from a last zero-cross event having a duration equal to a difference between an established time based upon the stored time interval and a first time. If a new zero-cross event is not detected within the established time, switching of the PWM driving signal may be disabled for a time having a maximum duration equal to a second time or until a new zero-cross event is detected.

Abstract: A circuit compares a first voltage and a second voltage using a comparator. The comparator has a current divider for dividing a bias current in accordance with the values of the first and second voltages, and for providing two currents. The comparator also has a current differentiation circuit for receiving the two currents and providing an output signal dependent upon the difference between the currents. At least one of the current divider and current differentiation circuits are arranged to weight one of the two currents with respect to the other current so that the output signal is only provided when the difference between the first and second voltages exceeds an offset value. A bias generator is provided which includes a second comparator having similar components in the same configuration as the comparator.

Abstract: A process for making a DRAM-type cell includes growing layers of silicon germanium and layers of silicon, by epitaxy from a silicon substrate; superposing a first layer of N+ doped silicon and a second layer of P doped silicon; and forming a transistor on the silicon substrate. The method also includes etching a trench in the extension of the transistor to provide an access to the silicon germanium layers relative to the silicon layers over a pre-set depth to form lateral cavities, and forming a capacitor in the trench and in the lateral cavities.

Abstract: The method of filtering data concerning an electronic program guide (EPG) in a television receiver having a device for automatically searching television channels includes supplying a list of CNI codes of all or some of the channels received by the television receiver to a memory. The method includes obtaining, from the SUMMARY of the guide, a MODIFIED SUMMARY containing only the information of the SUMMARY concerning all or some of the channels received by the television receiver, and recording only the data blocks of the CONTENTS of the guide in a memory when they correspond to all or some of the channels received by the television receiver.

Abstract: A generator producing a clock signal whose frequency depends on a control voltage includes a comparator for comparing a period of the clock signal with a desired period, and for providing at least one first control signal based upon the comparison. The generator includes a sampler circuit for sampling the first control signal, and for producing a first sampled control signal. The generator also includes a voltage generator for providing the variable control voltage as a function of the first sampled control signal.

Abstract: A method for forming an conductive interconnection in an electronic semiconductor device includes forming a layer of insulating material on a substrate of semiconductor material having a contact region therein, and forming a first opening through the layer of insulating material to expose the contact region. The first opening is filled with a material to form a first connection element. A first layer comprising a first removable conductive material is formed adjacent the layer of insulating material and the first connection element. The method further includes forming a second opening in the first layer to expose the first connection element, and filling the second opening with the material to form a second connection element. The first removable conductive material is removed except for a portion underlying the second connection element to expose the layer of insulating material. The areas left free after removing the first removable conductive material are filled with a dielectric material.

Abstract: A switching control method for level shifter includes a phase of de-selection of a high voltage value at an output terminal of the shifter using a selection signal. The de-selection phase may include starting the de-selection by bringing the selection signal to a low value; de-activating by way of the selection signal, the generation of a high-voltage signal being supplied to the shifter, and a reference voltage signal; computing the difference between an internal voltage signal of the shifter and the reference voltage signal; generating a control signal when the difference is found to be less than a threshold voltage value; and applying the selection signal to an input terminal of the shifter in the presence of the control signal.

Abstract: A pair of complementary current sources includes a reference current source, and two complementary current mirrors having the same number of branches provided with bipolar mirror transistors. The bases of the mirror transistors of the complementary mirrors are connected to a common node. One of the complementary mirrors is connected to the reference source. An intermediate current mirror includes a first slave branch connected to the other complementary current mirror, a second slave branch connected to the reference source, and a master branch connected to the output of a trimming circuit for trimming the complementary currents for substantially equalizing the base currents of the mirror transistors of the complementary current mirrors. The input of the trimming circuit is connected to the common node.

Abstract: A high bit density, high speed, via and metal BE type programmable ROM core cell architecture for storing large amounts of non-volatile data and having a relatively fast turn around time is provided. The ROM core cell may include memory cells organized in rows and columns where each of the memory cells includes three transistors and two bit lines. The arrangement between the three transistors and two bit lines may be such that each of the memory cells is capable of storing four bits of data.

Abstract: A field effect transistor having a variable doping profile is presented. The field effect transistor is integrated on a semiconductor substrate with a respective active area of the substrate including a source and drain region. A channel region is interposed between the source and drain regions and has a predefined nominal width. The effective width of the channel region is defined by a variable doping profile.

Abstract: A control device for a vehicle engine includes a memory unit for storing engine configuration parameters, a processing unit for sending control signals to the engine in accordance with the configuration parameters, and an input/output unit connectible to an external computer to modify the configuration parameters. The control device includes a first portion and a second portion of the memory unit, with each portion being alternately used in an active state for storing a current version of the configuration parameters or in an inactive state for the writing of a new version of the configuration parameters. The processing unit accesses the portion which is in the active state for reading, and the input/output unit accesses the portion which is in the inactive state for writing. An interconnection unit selectively switches one of the portions to the active state and the other of the portions to the inactive state.

Abstract: A driving circuit for electronically switched motors is provided. The driving circuit includes a supply voltage rectifying stage for providing a rectified supply voltage, first switching means for switching state based on output of a first control block, magnetic means for providing a magnetic flux according to the state of the first switching means, transmission diodes for transmitting an exciting current that flows through the magnetic means, first energy storing means for storing the exciting current, an energy return stage for transferring the energy stored in the first energy storing means to the rectifying stage, and energetic conversion means for receiving the energy stored in the energy storing means through second switching means controlled by a second control block, so as to provide a current as sinusoidal as possible.

Abstract: A voltage regulator having a comparator with an output terminal that is the output of the regulator, terminals for connection to a voltage supply, a source of a reference voltage connected to an input terminal of the comparator, and a feedback circuit connected between the output terminal and the other input terminal of the comparator. To prevent transients upon the transition from the standby state to the active state, there is provided a second reference-voltage source that provides a reference voltage substantially equal to that of the first source, a switch for connecting the second source to the other input terminal of the comparator, and a control circuit that can activate the supply of the regulator and can close the switch for a predetermined period of time when the supply of the regulator is activated.

Abstract: A noise compensating device in a discrete time control system, such as a R/W system for hard disks, including: a control loop generating a first timing signal, a signal indicative of a quantity to be controlled, and a control signal, which have a first frequency; and an open loop control line which generates a compensation signal synchronous with the control signal and includes a sensor. The sensor includes a sensing element, generating an analog signal, an acquisition stage, connected to the sensing element and generating a disturbance measure signal correlated to the analog signal and synchronous with the control signal, and a synchronization stage. The synchronization stage includes a frequency generator having an input receiving the first timing signal and a first and a second output connected to the acquisition stage and generating, respectively, a second timing signal and a third timing signal.

Abstract: A driving circuit for piezoelectric actuators comprises a chip of semiconductor material integrating both an interface circuit receiving at input a control signal generated by a control logic unit, and a power circuit driving the piezoelectric actuators. The power circuit is directly connected to the output of the interface circuit.

Abstract: Fully-differential, switched-capacitor circuit having a first and second input terminal, and including: an operational amplifier having a first and a second differential input, a first and a second output terminal and a bias control terminal; a feedback network, connected between the differential outputs and the input terminals, and having intermediate nodes connected to the differential inputs of the operational amplifier; and a control circuit, including a detection network and an error amplifier. The error amplifier has a first input receiving a desired common-mode voltage, and an output connected to the bias control terminal and supplying a control voltage. The detection network has a first and a second input connected directly, respectively, to the second input terminal of the operational amplifier, and an output connected to a second input of the error amplifier, and supplying a common-mode drive voltage.

Abstract: A method of assessing the neuro-psycho-physical condition of a person includes acquiring, by a self-contained hand held instrumentation, reaction times, execution times and ergometric data of actions performed by the person carrying out a certain test. This test includes processing the time data and the ergometric data for calculating the power exerted in performing each action. Data on the reaction time and the exerted power is processed on the basis of certain software to produce information on the neuro-psycho-physical condition. The ergometric data and reaction time data are processed by a fuzzy logic processor. The hand held instrument may optionally include also motion and voice articulation classifiers.

Abstract: A comparator circuit with comparing means for comparing first and second voltages, has current source circuitry for providing current to said comparing means, said current source circuitry having an input for receiving a clock signal having first and second states, whereby the comparing means starts to compare the first and second voltages when the clock signal makes a transition from the first state to the second state; and means for determining when said comparing means has completed a comparison of said first and second voltages and for switching off said current source circuitry and hence said comparing means when said comparison has been completed

Abstract: A slope control device for an electric data transmission system having a first line and a second line for differentially transmitting binary data pulses in such a manner that a first logic value of the data pulses has a high potential on the first line and a low potential on the second line associated therewith and a second logic value of the data pulses has a low potential on the first line and a high potential on the second line associated therewith, said slope control device being designed such that it regulates the slope steepness of the potential curve of a first one of both lines to a desired value; compares the slope steepness of the potential curve on one line to the slope steepness of the potential curve on the other line; and compares the slope steepness of the potential curve of the second line as a function of the comparison result.

Abstract: A non-volatile memory device with configurable row redundancy includes a non-volatile memory having a matrix of memory cells and a matrix of redundant memory cells, both organized into rows and columns. The memory device also includes row and column decoding circuits; read and modify circuits for reading and modifying data stored in the memory cells; and at least one associative memory matrix, also organized into rows and columns, able to store the addresses of faulty rows, and control circuits for controlling the associative memory matrix. The memory device further includes a circuit for recognizing and comparing selected row addresses with faulty row addresses contained in the associative memory matrix, such as to produce de-selection of the faulty row and selection of the corresponding redundant cell row in the event of a valid recognition; and a configuration register, also comprising a matrix of non-volatile memory cells, and associated control circuits.