Abstract: A dynamic random access memory (DRAM) includes a bit line pair, including a first bit line and a second bit line. Memory cells and a sense amplifier are coupled to the bit lines. A first characterization cell is coupled between the first bit line and a first reference supply line. The first characterization cell includes a capacitor. Similarly, a second characterization cell is coupled between the first bit line and the first reference supply line. The second characterization cell also includes a capacitor but preferably with a different capacitance. In the preferred embodiment, similar characterization cells are coupled to the second bit line.

Abstract: Presented is a circuit and method capable to digitally control and, in particular, to control the switching of one or two MOSFETs used as rectifiers in switched mode power supply isolated topologies. Basic circuit implementation of the presented technique is also introduced. A controller has a fixed frequency square wave signal main clock input, generically switching from a low to a high value in two different time intervals. The controller has one or two square wave outputs, swinging from low to high in phase or in opposite with respect to the clock signal. The digital control method is able to generate output signals timed to anticipate output transitions from high to low level with respect to the clock signal transitions. In the control scheme, one or two other secondary inputs set the amount of anticipation time of the respective transitions of the outputs.

Abstract: A positioning system for a read/write head of a disk drive includes a rotatable data disk, a read/write head movable over the disk, a voice coil motor (VCM) connected to the head and a source of digital position signals. A control circuit includes means for generating a VCM control current, a sensor for sensing the VCM current and an amplifier having an inverting input connected to a reference voltage source through a resistor and to a sensor output, a non-inverting input connected to the source of digital position signals through a DAC and an output connected to an input of the drive means.

Abstract: Presented is a high-efficiency CMOS voltage shifter including a differential cell circuit portion powered between first and second supply voltage references, and a first pair of transistors connected into a cascode configuration. Also included is a first divider of the first supply voltage reference for generating a reference voltage value on a first internal circuit node, which is connected to the gate terminals of the transistors in the first pair. The voltage shifter further includes a second divider of the first supply voltage reference for controlling the value of the reference voltage by means of a control circuit portion acting on the first divider.

Abstract: For use in a data processor comprising an instruction execution pipeline comprising N processing stages, a system and method of encoding constant operands is disclosed. The system comprises a constant generator unit that is capable of generating both short constant operands and long constant operands. The constant generator unit extracts the bits of a short constant operand from an instruction syllable and right justifies the bits in an output syllable. For long constant operands, the constant generator unit extracts K low order bits from an instruction syllable and T high order bits from an extension syllable. The right justified K low order bits and the T high order bits are combined to represent the long constant operand in one output syllable. In response to the status of op code bits located within a constant generation instruction, the constant generator unit enables and disables multiplexers to automatically generate the appropriate short or long constant operand.

Abstract: A multipurpose interlaced memory device functions in two different modes, synchronous and asynchronous. The memory uses a circuit for detecting address transitions by acting as a synchronous clock of the system for letting the control circuit of the memory device recognize the required access mode by enabling a comparison of the currently input external address with the one stored in the address counters of the two banks of memory cells. The memory device includes a buffer for outputting data. The buffer includes a circuit for pre-charging the output nodes to an intermediate voltage between the voltages corresponding to the two possible logic states, thus reducing noise and improving transfer time.

Abstract: A device for generating synchronous numeric signals, including a reference generating device supplying a reference signal and a first timing signal, both having a reference frequency; and a timed generating device supplying a synchronized signal having the reference frequency. The device further includes a synchronization stage generating a second timing signal having a first controlled frequency correlated to the reference frequency, and phase synchronization pulses having the first frequency and a preset delay programmable with respect to the first timing signal.

Abstract: A micro-controller is connected between a hardware-based adaptive differential pulse code modulation (ADPCM) decoder and a read only memory (ROM) storing both micro-controller programming instructions and ADPCM encoded source file data. A micro-controller architecture implements time multiplexed ROM addressing driven by a two phase clock signal. In an instruction phase, a program counter supplies ROM address(es) for retrieving micro-controller programming instructions. In a decoder phase, an address counter supplies ROM address (es) for retrieving portions of the ADPCM encoded source file data. ADPCM encoded source file data extracted from the ROM in the decoder phase of the clock signal is delivered to the decoder for processing during the subsequent instruction phase of the clock signal. The selection between program counter and address counter supplied addresses for application to the ROM is made by a two phase clock signal driven multiplexer.

Abstract: A method of improving the signal/noise ratio of a sigma-delta modulator during the re-establishment of its stability that includes: defining a bit sequence corresponding to a state of instability of the modulator, monitoring the flow of bits output by the modulator to check whether it contains the instability bit sequence, and resetting the modulator to zero if the instability bit sequence is detected at the output. To ensure a high signal/noise ratio of the modulator even during the detection and re-establishment of stability, the method also includes: delaying the flow of bits output by the modulator at least for the time required to detect the instability bit sequence and modifying the output bit sequence during the delay period by replacing it with a predetermined bit sequence.

Abstract: A radiation hardened memory device having static random access memory cells includes active gate isolation structures to prevent leakage currents between active regions formed adjacent to each other on a substrate. The active gate isolation structure includes a gate oxide and polycrystalline silicon gate layer electrically coupled to a voltage terminal resulting in an active gate isolation structure that prevents a conductive channel extending from adjacent active regions from forming. The gate oxide of the active gate isolation structures is relatively thin compared to the conventional oxide isolation regions and thus, will be less susceptible to any adverse influence from trapped charges caused by radiation exposure.

Abstract: An electronic thermal protection circuit is for high currents which can occur in the start-up phase in lighting converters. The circuit is associated with a power device having an output terminal connected to an electric load and at least one control terminal receiving a predetermined driving current value by a driving circuit portion. Advantageously, an integrated temperature sensor is provided to detect the temperature of the power device, and an output stage is connected downstream of the sensor to switch off the driving circuit portion when a predetermined operation temperature is exceeded.

Abstract: A nonvolatile memory having a NOR architecture has a memory array including a plurality of memory cells arranged in rows and columns in NOR configuration, the memory cells arranged on a same column being connected to one of a plurality of bit lines; and a column decoder. The column decoder comprises a plurality of selection stages, each of which is connected to respective bit lines and receives first bit line addressing signals. The selection stages comprise word programming selectors controlled by the first bit line addressing signals and supplying a programming voltage to only one of the bit lines of each selection stage. Each selection stage moreover comprises a string programming selection circuit controlled by second bit line addressing signals thereby simultaneously supplying the programming voltage to a plurality of the bit lines of each selection stage.

Abstract: To increase the facing surface and thus the coupling between the floating gate and control gate regions of a memory cell, the floating gate and control gate regions have a width that is not constant in different section planes parallel to a longitudinal section plane extending through the source and drain regions of the cell. In particular, the width of the floating gate and control gate regions is smallest in the longitudinal section plane and increases linearly in successive parallel section planes moving away from the longitudinal section plane.

Abstract: A microcomputer comprises an integrated circuit device with processor and memory and communication links arranged to provide non-shared connections to similar links of other microcomputers. The communication links include message synchronisation and permit creation of networks of microcomputers with rapid communication between concurrent processes on the same or different microcomputers.

Abstract: An integrated circuit is provided that includes a first internal circuit using a first internal clock signal whose first edges are active. The first internal circuit includes a test cell having an input and an output, a first transmission line connected to the input of the test cell, and a second transmission line connected to the output of the test cell. The test cell includes first and second latches and a selection circuit. The first latch stores either information on the first transmission line or information received from another test cell, and the second latch selectively receives the information stored in the first latch. The selection circuit provides to the second transmission line either the information on the first transmission line or the information stored in the second latch. The test cell also includes means for storing the information on the first transmission line in the second latch during second edges of the first internal clock signal when the test cell is not in test mode.

Abstract: A method of equalizing a read channel of a mass magnetic memory device comprises attenuating the low frequencies of the spectrum of the analog signal originating from an electromagnetic read transducer without boosting the high frequency harmonic components of the spectrum. The low frequencies of the spectrum of the analog input signal are attenuated with a low pass filter of an order in a range from 6 to 8 and a boost is implemented by introducing two real and opposed zeroes in the transfer function of the filter without altering the group delay.

Abstract: A system and method for communication between a CPU and on-chip modules in an integrated circuit and off-chip devices is disclosed. A path on the integrated circuit allows for packet traffic to flow between the CPU and modules. In some embodiments the path is a data bus. Various types of packets are used, but each include a destination indicator to indicate the required destination device connected to the path. Data transfer packets are used for memory access operations. Normal event packets form prioritized interrupts wherein the recipient CPU or module respond to the event packet depending on relative priorities associated with other packets sent to the recipient device. Special event packets form command control signals that must be acted on by the recipient device when the special event packet is received.

Abstract: A low stress, low profile, cavity down wire bond or flip-chip BGA package is formed by injection molding or thermosetting of liquid crystal plastic (LCP) to form a die carrier including a polymer solder grid array (PSGA) of standoff posts formed during molding of the die carrier. The standoff posts are coated with copper during plating of the die carrier, on the surfaces of which conductive traces are etched from the standoff posts into a die cavity, including on the sidewalls of the die cavity, to wire bond sites or small solderable areas at the bottom of the cavity. After mounting of a wire bond or flip-chip integrated circuit die within the die cavity of the die carrier, the packaged integrated circuit is mounted on a main printed circuit board (PCB) substrate utilizing conductive paste to electrically connect the standoff posts to conductive solderable areas on the main PCB substrate.

Abstract: The compressed data of an auxiliary stream of data, defining an auxiliary image, is decoded on the fly during the display of each main image into which this auxiliary image is to be inset. The data is decoded to deliver luminance and chrominance values intended to be mixed with the luminance and chrominance values of the counterpart pixels of the main image being displayed, in succession during each decoding of the auxiliary image and for the successive pixels of this auxiliary image.

Abstract: A switching regulator circuit produces a varying reference voltage with temperature and includes at least one band-gap generator for supplying a power stage through an error amplifier and a comparator. The error amplifier is also supplied a regulated voltage which may be produced by the regulator itself. The at least one band-gap generator includes a plurality of band-gap generators being supplied by the regulated voltage and input a fraction of the regulated voltage through a voltage divider. The respective outputs of the band-gap generators are connected to a logic network which has an output connected to the power stage. The error amplifier and comparator may be included within each respective band-gap generator.