Abstract: A reading method for non-volatile memory cells is which includes a first step in which a memory cell of the matrix is selected by the row decoder and by the column multiplexer, a second step of preload and equalization during which the voltage on the drain electrode of the selected memory cell reaches a defined value and a third step during which the selected cell is read with a sensing ratio depending on the reading voltage of said cell. Moreover a device for the reading of the cells is described, which comprises a modulation branch with at least one modulation transistor and a load generator associated with said modulation transistor in such a way to modulate analogous the transconductance of one of the two load transistors as a function of the reading voltage of the memory cell.

Abstract: A multi-carrier transmission system, such as a DMT system. A receiver must be able to recover a sampling clock that is very accurately synchronized to a transmitter sampling clock. Typically, synchronization is achieved by using a reserved carrier, the pilot carrier, which is transmitted with a fixed phase. The receiver sampling clock is then phase locked to the pilot carrier. Frame timing can be recovered by using a correlation technique. Thus an improved method of recovering a sample clock and phase locking the sampling clock to a pilot carrier is provided.

Abstract: A comparator circuit for positive and negative signals having zero consumption and suitable for devices with a single positive power supply includes a first and second comparator connected in parallel and receiving a common input signal and, respectively, a first positive threshold voltage and a second negative threshold voltage. The comparator circuit further includes a first logic circuit cascade-connected to the first and second comparators. The first and second comparators are respectively suitable to detect the crossing on the part of the input signal of the first and second threshold voltages. The second comparator is provided by n-channel and p-channel MOS transistors of the enhancement type. The comparator circuit also includes a second logic circuit cascade-connected to the first logic circuit, and a monostable circuit connected to the second logic circuit.

Abstract: Flow process for producing non-volatile memories with differentiated removal of the sacrificial oxide in the NO-DPCC diagram including a series of steps that permit the removal of the oxide in two distinct moments from the matrix area and from the circuitry area. In this manner the active circuitry areas are preserved from the danger of breaking the tunnel oxide, thus avoiding the degradation of the quality of the oxides and increasing, in addition, the level of reliability of the device itself.

Abstract: A device for detecting and correcting errors in error correction coded (ECC) data blocks that are read sequentially from a DVD medium is disclosed. Each ECC data block is defined as a two dimensional block of a plurality of columns and rows. Each of the ECC data blocks is read from the DVD medium sequentially in rows. The device includes row correction circuitry, a buffer, column correction circuitry, and repeat correction circuitry. The row correction circuitry is configured to sequentially receive the rows of an ECC data block for detecting and correcting up to a first predetermined number of errors in each of the received rows. The buffer is coupled to the row correction circuitry for receiving the error corrected rows of the ECC data block as a receiving buffer. The buffer also stores the ECC data block as a correction buffer when all the rows of the ECC data block have received.

Abstract: A process for manufacturing a SOI wafer with buried oxide regions without cusps that includes forming, in a wafer of monocrystalline semiconductor material, trenches extending between, and delimiting laterally, protruding regions; forming masking regions, implanted with nitrogen ions, the masking regions surrounding completely the tips of the protruding regions; and forming retarding regions on the bottom of the trenches, wherein nitrogen is implanted at a lower dose than the masking regions. A thermal oxidation is then carried out and starts at the bottom portion of the protruding regions and then proceeds downwards; thereby, a continuous region of buried oxide is formed and is overlaid by non-oxidized regions corresponding to the tips of the protruding regions and forming nucleus regions for a subsequent epitaxial growth.

Abstract: Presented is a low supply voltage oscillator circuit having at least one capacitor to be controlled, connected between first and second voltage references, and a circuit for charging and discharging the capacitor to be controlled. The oscillator circuit also includes at least first and second stages having symmetrical structures in a mirror-image configuration and being connected between the first voltage reference and the second voltage reference and connected together through a memory element. The oscillator circuit also includes respective primary switches for alternately charging the capacitors in a controlled fashion.

Abstract: A device for the regeneration of a clock signal from an external serial bus includes a ring oscillator and counter. The ring oscillator provides n phases of a clock signal. Of these n phases, one phase is used as a reference and is applied to the counter. It is thus possible to count the number of entire reference clock signal periods between a first pulse and a second pulse received from the bus. In reading the state of the phases in the oscillator upon reception of the second pulse, a determination is made for a current phase corresponding to the phase delay between the reference clock signal and the second pulse of the bus. By using a regeneration device that also includes a ring oscillator and a counter, it is possible to regenerate the clock signal of the bus with high precision.

Abstract: A method for manufacturing memory points including control and floating gates, including the steps of: delimiting at the surface of the substrate an active region by insulation areas; forming a first insulating layer; opening a window in the first insulating layer to partially expose the entire width of the active region and a portion of the insulating areas; forming a second very thin insulating layer; depositing a first conductive material; forming a third insulating layer; and depositing a second conductive material, and further including a step of etching the first and second conductors and the third, second, and first insulating layers according to a same contour to expose the active region and the insulation areas in the vicinity of the borders between the active region and the insulation areas.

Abstract: A low pass filter with programmable equalization includes at least one biquadratic cell and a converter of the input voltage into a current, proportional to the derivative of the input voltage, that is injected on a node of the biquadratic cell to introduce two real and opposed zeros in the transfer function of the filter. The low pass filter includes two structurally similar circuits functionally connected in cascade. Each circuit includes a biquadratic cell and an input stage having two outputs injecting, through a first current output, the current to an input capacitor of the respective biquadratic cell, by a direct coupling in a first of the two circuits and in an inverted manner in the second of the two circuits. A second voltage output is coupled to an input of the respective biquadratic cell.

Abstract: A miss detector for a content addressable memory has plural input lines connected across points with the memory output lines. The detector input lines are disposed in pairs of true and false lines, and gating circuitry gates together the true and false pairs to provide a miss error message.

Abstract: The distance sensor has a capacitive element (33, 34) in turn having a first plate (23) which is positioned facing a second plate (18) whose distance is to be measured. In the case of fingerprinting, the second plate is defined directly by the skin surface of the finger being printed. The sensor includes an inverting amplifier (13), between the input and output of which the capacitive element (33, 34) is connected to form a negative feedback branch. By supplying an electric charge step to the input of the inverting amplifier, a voltage step directly proportional to the distance being measured is obtained at the output.

Abstract: The n-channel VDMOS transistor is formed in an n-type active region of an integrated circuit with junction isolation. To prevent over-voltages between source and gate which could damage or destroy the gate dielectric, a p-channel MOS transistor is formed in the same active region and has its gate electrode connected to the gate electrode of the VDMOS transistor, its source region in common with the source region of the VDMOS transistor, and its drain region connected to the p-type junction-isolation region. The p-channel MOS transistor has a threshold voltage below the breakdown voltage of the gate dielectric of the VDMOS transistor so that it acts as a voltage limiter.

Abstract: A ROM including memory cells, the programmed cells being formed of a transistor connected between a bit line and a supply potential, the cells being organized in sets of at least one column coupled to one sense amplifier per set. The cell programming is inverted with respect to a desired programming only in specific sets where the desired programming would result in a number of programmed cells greater than the number of unprogrammed cells, the logic state provided by the sense amplifiers associated with the specific sets being inverted.

Abstract: A method for controlling an electromagnetic actuator having an arm connected thereto uses a circuit that temporarily places in a high impedance state output nodes connected to a winding of the electromagnetic actuator. A detected BEMF is compared with a lower threshold and an upper threshold. Current in the electromagnetic actuator is monitored and controlled. A current pulse is provided to the electromagnetic actuator based upon the comparison of the detected BEMF with the lower and upper thresholds. The respective amplitudes of successively provided current pulses having a same polarity are progressively increased, and an amplitude of a provided current pulse having a polarity opposite a polarity of a preceding current pulse is decreased. The amplitude of the driving current pulses provided to the winding of the electromagnetic actuator advantageously adapts automatically to varying frictional conditions, or to any other cause of variation of the mechanical load of the actuator.

Abstract: The memory cell is formed in a body of a P-type semiconductor material forming a channel region and housing N-type drain and source regions at two opposite sides of the channel region. A floating gate region extends above the channel region. A P-type charge injection region extends in the body contiguously to the drain region, at least in part between the channel region and the drain region. An N-type base region extends between the drain region, the charge injection region, and the channel region. The charge injection region and the drain region are biased by special contact regions so as to forward bias the PN junction formed by the charge injection region and the base region. The holes thus generated in the charge injection region are directly injected through the base region into the body, where they generate, by impact, electrons that are injected towards the floating gate region.

Abstract: The ROM memory cell, not decodable by visual inspection comprises a substrate of semiconductor material having a first conductivity type, in particular P−. A first MOS device having a first threshold voltage is formed in a first portion of the substrate, and a MOS device having a second threshold voltage, greater than the first threshold voltage, is formed in a second portion of the substrate adjacent to the first portion. The second MOS device is a diode reverse biased during a reading phase of the ROM memory cell and comprises a source region having the first conductivity type and a drain region having a second conductivity type. The source region has a level of doping higher than that of the substrate.

Abstract: A word recognition device uses an associative memory to store a plurality of coded words in such a way that a weight is associated with each character of the alphabet of the stored words, wherein equal weights correspond to equal characters. To perform the recognition, a dictionary of words is first chosen; this is stored in the associative memory according to a pre-determined code; a string of characters which correspond to a word to be recognized is received; a sequence of weights corresponding to the string of characters received is supplied to the associative memory; the distance between the word to be recognized and at least some of the stored words is calculated in parallel as the sum of the difference between the weights of each character of the word to be recognized and the weights of each character of the stored words; the minimum distance is identified; and the word stored in the associative memory having the minimum distance is stored.

Abstract: A lead-frame for semiconductor devices having a mold with at least one air vent for the resin to seep out of during its injecting into the mold, the air vent being positioned between the upper and lower surface of the frame, wherein the frame provides a through hole positioned at the outlet of the air vent so that, when the resin has solidified, it forms a flash which is in coherence with the surface of the frame.

Abstract: A decoupling circuit for decoupling conduction lines from each other, the circuit including at least one pass gate element having conduction terminals connected to the conduction lines and having at least one control terminal. The decoupling circuit includes at least one protection circuit inserted between the control terminal and at least one of the conduction lines, and including at least one protection transistor connected to the control terminal and to the at least one conduction line, and configured to take in a disturbing signal passing through the pass gate element (N1) to properly decouple the conduction lines from each other on the occurrence of a disturbing condition.