Abstract: A device for the programming of cells of an electrically programmable non-volatile memory. The device comprising a first reference input for receiving an erase signal for erasing one or more memory cells in the non-volatile memory and a second reference input for receiving an programming signal for programming one or more memory cells in the non-volatile memory. A regulation circuit coupled to the first reference input and coupled to the second reference input for regulating the magnitude of an erasure signal and for regulating the magnitude of a programming signal so that an electric field of approximate equal absolute magnitude is created on the floating gate of one or more memory cells during an erase type operation and an programming type operation.

Abstract: Methods of forming, in an integrated circuit, aluminum-silicon contacts with a barrier layer is disclosed. The barrier layer is enhanced by the provision of titanium oxynitride layers adjacent the silicide film formed at the exposed silicon at the bottom of the contact. The titanium oxynitride may be formed by depositing a low density titanium nitride film over a titanium metal layer that is in contact with the silicon in the contact; subsequent exposure to air allows a relatively large amount of oxygen and nitrogen to enter the titanium nitride. A rapid thermal anneal (RTA) both causes silicidation at the contact location and also results in the oxygen and nitrogen being gettered to what was previously the titanium/titanium nitride interface, where the oxygen and nitrogen react with the titanium metal and nitrogen in the, atmosphere to form titanium oxynitride. The low density titanium nitride also densifies during the RTA.

Abstract: A serial input/output memory is able to read data in the memory upon reception of a partial read address in which there are N least significant bits lacking to form a complete address. The read-ahead step includes: simultaneously reading the P first bits of M words of the memory having the same partial address; when the received address is complete, selecting the P first bits of the word designated by the complete address and delivering these bits at the serial output of the memory; reading P following bits of the word designated by the complete address during the delivery of P previous bits and delivering these bits at the serial output of the memory when the P previous bits are delivered.

Abstract: An integrated circuit memory includes a FLASH memory including a circuit for recording a word presented on its input without the possibility of recording simultaneously several words in parallel. The integrated circuit memory may include a buffer memory with a sufficient capacity to store a plurality of words, the output of which is coupled to the input of the FLASH memory. A circuit is also included for recording into the buffer memory a series of words to be recorded into the FLASH memory and recording into the FLASH memory the words first recorded into the buffer memory.

Abstract: A device for the regeneration of a clock signal from an external serial bus includes a ring oscillator and counter. The ring oscillator provides n phases of a clock signal. Of these n phases, one phase is used as a reference and is applied to the counter. It is thus possible to count the number of entire reference clock signal periods between a first pulse and a second pulse received from the bus. In reading the state of the phases in the oscillator upon reception of the second pulse, a determination is made for a current phase corresponding to the phase delay between the reference clock signal and the second pulse of the bus. By using a regeneration device that also includes a ring oscillator and a counter, it is possible to regenerate the clock signal of the bus with high precision.

Abstract: A switching output power stage, including a power switching device for the supply line and a complementary power switching device for the ground rail driven in phase opposition by a pulse width modulated (PWM) drive signal, is provided with sensors detecting a substantial turn-off state of each of the two power switching devices and generating a pair of logic signals. A combinatory logic circuit combines the drive signal and the pair of logic signals and generates a pair of driving signals of opposite phase for the respective power switching devices. The switching to a turn-on state of any of the two power devices is enabled upon verifying a substantially attained turn-off state by the device complementary to the device commanded to turn-on, irrespective of the process spread and of changes of temperature load conditions and of configuration of a plurality of output stages of a multichannel amplifier.

Abstract: The method is for forming porous silicon in a silicon substrate, in particular for improving the quality factor of an inductive circuit produced on a silicon semiconductor wafer which also incorporates integrated transistors. The rear face of the wafer, already incorporating the transistors and the inductive circuit on its front face, is placed in contact with an acid electrolyte containing hydrofluoric acid and at least one other acid. An anodic oxidation of the silicon of the wafer at the rear face is carried out so as to convert this silicon into porous silicon over a predetermined height from the rear face which is in contact with the electrolyte.

Abstract: A digital signal processing system, including an analog-to-digital converter adapted to provide at least n-bit samples to a processor, and range selection circuitry for stepwise adjusting the range of the analog-to-digital converter to the amplitude of an input signal and for shifting the position of the n-bit samples on the processor bus according to the selected range.

Abstract: A voltage level shifter and an associated level shifting method for shifting from a low voltage input signal to a high voltage output signal are discussed. The level shifter includes a voltage shifting stage having first and second control input nodes and an output node at which the output signal is produced based on control signals received at the control input nodes. The level shifter also includes first and second input inverters coupled in series between the input node and the first control input node; and a third input inverter coupled between the input node and the second control input node. The second inverter can include complementary first and second transistors each with control terminals coupled to an output of the first inverter. The first transistor has a first terminal coupled to the input node and is structured to pass the input signal to the first control input node based on a logic value of a signal output by the first inverter.

Abstract: The present invention relates to a digital filter for a phase-locked loop receiving at least one input signal having a predetermined period, including an element of accumulation of frequency values receiving the output of a phase detector; and an element of accumulation of phase values receiving a weighted sum of the output of the phase detector and of the content of the element of accumulation of frequency values. Each of the accumulation elements includes several frequency or phase value storage locations, circuitry being provided for successively making operative the storage locations in the phase-locked loop during a period of the input signal.

Abstract: An electronic device battery pack for a battery requiring cycling to prolong lifetime is divided into at least two parallel cells for which the charging state is automatically maintained. When external power is available and one or more cells is substantially discharged, the substantially discharged cell(s) are selected one at a time to be fully drained and recharged. A partially discharged but not substantially discharged cell will be left in that state until use of the electronic device has substantially discharged the cell. Once a cell has been recharged, the next substantially discharged cell is drained and recharged, and so on until all cells are fully charged. If the charging of a cell is interrupted by removal of the external power, another cell is utilized to provide power to the electronic device and recharging is resumed once the external power is restored.

Abstract: The present invention relates to a circuit for supplying a load from an approximately D.C. voltage obtained by rectifying an A.C. voltage, including means for extracting from the rectified A.C. voltage an information depending on a phase angle variation of the A.C. voltage, and a means for making the approximately D.C. load supply voltage independent from the phase angle variation of the A.C. voltage.

Abstract: The high-voltage bidirectional switch includes a controlled transistor having a first terminal and a second terminal set, respectively, at a first potential and at a second potential. The controlled transistor moreover includes a control terminal connected to a control block, which is in turn connected to a precharge block The controlled transistor has its bulk region connected to a biasing block which is in turn connected both to the precharge block and to the second terminal of the controlled transistor. The control block and the biasing block are moreover connected to a signal-generator block connected to a control unit.

Abstract: A bias circuit for read amplifier circuits for memories includes at least one first circuit branch formed by a first pair of MOS transistors connected between a supply voltage and ground. The first pair of MOS transistors includes a P-channel diode connected transistor and an N-channel transistor connected in series, with an enable transistor interposed therebetween. The first circuit branch drives a capacitive load for coupling to the supply voltage. The bias circuit further includes reference current amplifier circuit branches for amplifying a reference current which flows in the first circuit branch for charging the capacitive load. A circuit portion, which controls the charging current of the capacitive load, includes a feedback loop between the reference current amplifier circuit branches and the capacitive load.

Abstract: A method is provided for depositing aluminum thin film layers to form contacts in a semiconductor integrated circuit device. All or some of the deposition process occurs at relatively low deposition rates at a temperature which allows surface migration of the deposited aluminum atoms. Aluminum deposited under these conditions tends to fill contact vias without the formation of voids. The deposition step is periodically interrupted.

Abstract: A monolithically integrated selector for electrically programmable memory cell devices can be switched at an output terminal (OUT) between a high voltage (HV) and a low voltage (LV). It comprises a leg (N2, N1) of fast ground discharge (GND) from the output terminal, a discharge control leg (P1, N3, N4) driving the selector switching through a phase generator (PHG).

Abstract: A method is provided for carrying out a trimming operation on an integrated circuit having a trimming circuit portion which includes memory elements and a modification circuit for modifying the state of the memory elements, at least a first input or supply pin, an output pin, and a second supply pin. According to the method, a single pin is enabled to receive trimming data by biasing the pin to outside its operating range. A clock signal is obtained from a division of the bias potential of the pin, and the logic value of the trimming data is obtained from a different division of the bias potential of the pin. Serial acquisition of the data is enabled in accordance with the clock signal, and the data is transferred to the modification circuit.

Abstract: The method comprises forming an implantation screening layer of predetermined thickness on the wafer, forming, in the screening layer, a first rectilinear, elongate opening having a first width, and at least a second rectilinear, elongate opening substantially parallel to the first opening and having a second width smaller than the first width is formed on the screening layer. The wafer is then subjected to ion implantation with two ion beams directed in directions substantially perpendicular to the longitudinal axes of the openings and inclined to the surface of the wafer at predetermined angles so as to strike the openings from two opposite sides. The thickness of the screening layer, the widths of the openings, and the angles of inclination of the ion beams being selected in a manner such that the beams strike the base of the first opening for substantially uniform doping of the underlying area of the wafer, but do not strike the base of the second opening.

Abstract: An integrated circuit memory fabrication process and structure, in which salicidation is performed on the periphery (and optionally on the ground lines) of a memory chip, but not on the transistors of the memory cells.

Abstract: A method of protecting data in a semiconductor electronic memory, which includes using a protected memory portion within the matrix and respective dedicated decoding portions for storing, into the protected portion, a protection code without the address area of the matrix. The protection code can only be written and/or read through a command interpreter.