Abstract: The selection/deselection circuit is for non-volatile memory word lines having a decoding line connected between a supply voltage and ground, and including a series of decoding transistors of the same conductivity controlled by respective selection signals and at least a load transistor whose conductivity is opposite to the conductivity of the decoding transistors in series with the series of transistors and biased by a control voltage. The load transistor produces an activating or deactivating voltage of a memory word line, and a circuit for controlling the load transistor is provided. Such an auxiliary control circuit includes a sensing element in series with the decoding transistors and the load transistor for producing a sensing signal switching between a first value when only one memory line is actually selected and a second value when multiple memory word lines appear to be simultaneously selected. Also, an inverter receives the sensing signal and outputs a first signal.

Abstract: A circuit and method is disclosed for a memory cell for a static random access memory. The memory cell includes a pair of cross-coupled CMOS logic inverters that are connected together to form a latch, and a pair of p-channel transmission gate transistors that are connected to the logic inverters for selectively providing access to the latch. The layout of the memory cell includes a rectangular active area in which the p-channel transistors of the memory cell are located. The rectangular active area abuts a similar active area of an adjacent memory cell along a row of memory cells so as to form a single rectangular active area for the p-channel memory cell transistors. The rectangular active area reduces the occurrence of fabrication-related phenomena that adversely effect the performance of the memory cell.

Abstract: A substantially noise-free data input buffer for an asynchronous device, such as a static random access memory (SRAM). The input buffer generates either a logical true or complement output signal representation of a data input signal and includes timing circuitry to delay an edge transition on the output signal for a predetermined period of time in response to a signal edge transition appearing on the data input signal. The input buffer further includes edge transition detection (ETD) circuitry for generating an initialization signal in response to the generation of the data output signal.

Abstract: A control or adjusting circuit for a load, a desired signal is compared to an actual signal corresponding to the state of the load, and a PWM control signal is generated in a control signal generating circuit in accordance with the comparison result. The control signal opens and closes a current switch coupled to the load. For forming the PWM control signal, the contents of a ramp counter are compared to the contents of an up/down counter by means of a digital comparator. To obtain fast approximation of the two signals to each other in the case of strong deviations between the desired signal and the actual signal, the up/down counter is subjected to relatively rapid counting in case of high control deviations as compared to low control deviations. To this end, the up/down counter is operated with a clock signal of variable frequency that is produced by a voltage-controlled oscillator as a function of the difference between the desired signal and the actual signal.

Abstract: A circuit structure for semiconductor devices which are integrated on a semiconductor layer is provided. The structure comprises at least one MOS device and at least one capacitor element that has a bottom and a top electrode. The MOS device has conduction terminals formed in the semiconductor layer, as well as a control terminal covered with an overlying insulating layer of unreflowed oxide. The capacitor element is formed on the unreflowed oxide layer.

Abstract: A process for the manufacture of a non-volatile memory with memory cells arranged in word lines and columns in a matrix structure, with source lines extending parallel and intercalate to said lines, said source lines formed by active regions intercalated to field oxide zones, said process comprising steps for the definition of active areas of said columns of said matrix of non-volatile memory cells and the definition of said field oxide zones, subsequent steps for the definition of the lines of said matrix of non-volatile memory cells, and a following step for the definition of said source lines.

Abstract: A method of vapor phase epitaxy deposition of silicon on a silicon substrate on or in which exist areas containing dopants at high concentration, among which is boron, while avoiding a selfdoping of the epitaxial layer by boron, including the step of introducing a chlorinated gas, before the epitaxial deposition step, to etch the substrate across a thickness smaller than 100 nm.

Abstract: A pseudo-random number generator includes a first generator for producing a sawtooth waveform signal having a first frequency, and a second generator for producing a pulse signal having a second frequency. A sampling circuit samples the sawtooth waveform signal and the pulse signal for generating a sample signal of the sawtooth waveform signal at the second frequency. A coding circuit codes the amplitude of the sample signal to supply binary values. The pseudo-random number generator has applications in integrated circuits which are used in contact type or contactless IC cards.

Abstract: A method for fabricating a silicon-on-insulator (SOI) wafer that includes a monocrystalline silicon substrate with a doped region buried therein is provided. The method includes forming a plurality of trench-like openings extending from a surface of the substrate to the doped buried region, and selectively etching through the plurality of trench-like openings to change the doped buried region into a porous silicon region. The porous silicon region is oxidized to obtain an insulating region for the SOI wafer.

Abstract: A data output buffer includes an output node, and a first stage connected to the output node for providing a first control signal for precharging the output node to an intermediate voltage with respect to a voltage for switching the output node from a current logic state to a different logic state. A second stage is connected to the first stage and to the output buffer. The first and second stages are responsive to a second control signal for enabling output of new data. A precharge logic circuit precharges the output node to the intermediate voltage as a function of data last output, and as a function of first and second reset signals until a rising and falling edge of the data last output respectively crosses the intermediate voltage.

Abstract: An electronic device is formed on a chip of semiconductor material covered by a layer of insulating material. Metal interconnection elements form, on the insulating layer, connection pads to which a soldering material is applied. To permit good heat dissipation, the device has a metal plate partially incorporated in the insulating layer and having a surface which is coplanar with the pads and to which soldering material is applied. The electronic device is secured to a mounting substrate having a corresponding metal plate.

Abstract: A field-effect transistor structure wherein a single patterned thin film semiconductor layer: is monocrystalline, and epitaxially matched to and dielectrically isolated from an underlying body region, in channel locations; and is polycrystalline in source/drain locations which abut said channel locations.

Abstract: A device controller controls access to a device, such as a television, having a power input for receiving power and a data input for receiving control data. When in standby mode, the device controller disconnects the device from a power source, such as the AC mains of the building in which the device is situated. As a result, in standby mode only the device controller is powered, which uses much less power than prior art devices in standby mode. The device controller includes an input device structured to provide control data based on control instructions received from a user, a power switch coupled between a power source and the device power input, and a data coupler coupled to the device data input and structured to convert electrical data into non-electrical data and back to the electrical data for delivery to the device data input.

Abstract: Two improved process steps of eliminating cracks within TiN and/or BPSG layers after the RTP process are provided. The first is to provide a low deposition power, preferably below 6.5 KWH, and a high process pressure, preferably above 5.6 mTorr, to the TiN layer. No crack is found for this improved TiN deposition process when the RTP temperature rises from 450° C. to about 700° C. The second is to provide a low RTP temperature, preferably below 595° C., to the semiconductor wafer. No crack, again, is found by using this low RTP temperature.

Abstract: A protection circuit of a diagnostic output line (K-line) of a control unit for protection of the control unit in the event of a ground disconnection or of a “below ground” condition is provided. The diagnostic output line includes a first interface DMOS transistor with a source connected to ground and a drain coupled to the diagnostic output line through a second DMOS transistor with a source connected to the output line and a drain connected to the source of the first DMOS transistor. The protection circuit also includes a comparator for the voltage of the diagnostic output line with the potential of the ground node, and a two-input logic gate, whose output controls a current generator forcing a current, limited by a resistor, on the diagnostic output line.

Abstract: A circuit of electric arc generation from an A.C. voltage, includes circuitry for making the electric arc frequency substantially independent from possible amplitude variations of the A.C. voltage.

Abstract: A method for the in-writing verification of the threshold value of the multilevel cells suitable to memorize n bits each, that provides for the utilization of a sense amplifier containing a respective successive approximation register. An output signal of a comparison circuit provides for the loading of the datum to be programmed in the cell being selected, after which a programming pulse is applied and the comparison between the reference current corresponding to said datum and the current that flows in the cell is carried out. The application of the programming pulse and the performance of the comparison are then repeated until it is verified that the current of the cell is smaller than the reference current.

Abstract: A dynamic random access memory (DRAM) device is disclosed. The DRAM device includes a memory cell array having a twisted bit line architecture. The memory cell array includes at least one pair of redundant rows of memory cells. Redundant row decode circuitry is capable of configuring the pair of redundant rows to replace any one row of memory cells having a defect. Each pair of bit lines is coupled to a distinct memory cell from each redundant row of the redundant row pair so that both the true and complement version of a data value is maintained by the redundant row pair. Rows of reference cells are disconnected and/or disabled during a memory access operation involving the redundant row pair. The use of a pair of redundant rows of memory cells to replace a single row of memory cells having a defect substantially reduces the complexity of decode circuitry for enabling the rows of reference cells.

Abstract: A method of and system for providing user input to a computer captures a first finger position image at a first time and a second finger position image at a second time. The first and second finger position images each comprise a plurality of numerical gray scale values equal to or greater than zero. The system then subtracts the first finger position image from the second finger position image to obtain a composite image. The composite image has a first region comprising numerical values less than zero and a second region comprising numerical values greater than zero. The system provides X-Y input to the computer based upon the relative positions of first and second regions. The system further provides Z input to the computer based upon the relative sizes of said first and second regions.

Abstract: A non-volatile memory device organized with memory cells arranged by rows and columns in a matrix structure comprising source lines for memory cell groups. A switch is set between at least two rows or columns or source lines, which has two no pilotable terminals connected respectively to each one of the two rows or columns or source lines and a pilotable terminal connected to a logic circuitry. The switch allows a precharge of one of the two rows or columns or source lines by capacitive means associated to a each one of the two rows or columns or source lines after the other of the two rows or columns or source lines is connected to a higher voltage than that of said one of the two rows or columns or source lines.