Patents Assigned to STMicroelectronics
  • Publication number: 20250068335
    Abstract: System, method, and circuitry for generating content for a programmable computing device based on user-selected memory regions. Contiguous regions that share memory access attributes are merged, interleaved contiguous regions that share at least one nested attribute are defined into combined regions, and remaining regions are defined as separate independent regions. A memory protection unit (MPU) region size closest to a size of each defined region is identified. If the start address of each region aligns with the address structure of the MPU region size, then those regions are assigned to MPU regions having the MPU region size; otherwise, another MPU size that aligns with the size of the regions is selected and those regions are assigned to MPU regions having that size. Content is generated to configure settings of MPU regions of the programmable computing device for the merged contiguous regions, the combined region, and the independent regions.
    Type: Application
    Filed: November 12, 2024
    Publication date: February 27, 2025
    Applicant: STMicroelectronics (Grand Ouest) SAS
    Inventors: Frederic RUELLE, Michel JAOUEN
  • Patent number: 12237007
    Abstract: A circuit includes a memory array with SRAM cells connected in rows by word lines and in columns by bit lines. A row controller circuit simultaneously actuates, through a word line driver circuit for each row, word lines in parallel for an in-memory compute operation. A column processing circuit processes analog voltages developed on the bit lines in response to the simultaneous actuation to generate a decision output for the in-memory compute operation. A bit line clamping circuit includes a sensing circuit that compares the analog voltages on a given pair of bit lines to a threshold voltage. A voltage clamp circuit is actuated in response to the comparison to preclude the analog voltages on the given pair of bit lines from decreasing below a clamping voltage level.
    Type: Grant
    Filed: June 29, 2022
    Date of Patent: February 25, 2025
    Assignee: STMicroelectronics International N.V.
    Inventors: Kedar Janardan Dhori, Harsh Rawat, Promod Kumar, Nitin Chawla, Manuj Ayodhyawasi
  • Patent number: 12236000
    Abstract: Method for detecting the linear extraction of information in a processor using an instruction register for storing an instruction including an operation code. The method includes monitoring the instructions successively stored in the instruction register including decoding the operation codes, determining the number of consecutive operation codes encoding incremental branches, and generating a detection signal if the number is greater than or equal to a detection threshold.
    Type: Grant
    Filed: December 16, 2021
    Date of Patent: February 25, 2025
    Assignees: STMicroelectronics (Alps) SAS, STMicroelectronics (Grenoble 2) SAS
    Inventors: Diana Moisuc, Christophe Eichwald
  • Publication number: 20250063785
    Abstract: An electronic device includes a solid body of SiC having a surface and having a first conductivity type. A first implanted region and a second implanted region have a second conductivity type and extend into the solid body in a direction starting from the surface and delimit between them a surface portion of the solid body. A Schottky contact is on the surface and in direct contact with the surface portion. Ohmic contacts are on the surface and in direct contact with the first and second implanted regions. The solid body includes an epitaxial layer including the surface portion and a bulk portion. The surface portion houses a plurality of doped sub-regions which extend in succession one after another in the direction, are of the first conductivity type, and have a respective conductivity level higher than that of the bulk portion.
    Type: Application
    Filed: August 29, 2024
    Publication date: February 20, 2025
    Applicant: STMicroelectronics S.r.l.
    Inventors: Simone RASCUNÁ, Claudio CHIBBARO
  • Publication number: 20250061301
    Abstract: A debug method implemented by a first near field communication (NFC) device includes a step of storing, in a memory of the first NFC device, one or more parameters which are associated with the operation of the first NFC device during a communication with a second distant NFC device. The first NFC device then uses an answer to select (ATS) communication, sent in response to receipt of an answer to select (ATS) communication, to send the stored one or more parameters to the second distant NFC device.
    Type: Application
    Filed: August 12, 2024
    Publication date: February 20, 2025
    Applicant: STMicroelectronics International N.V.
    Inventors: Lucile MARGARIA, Philippe ALARY, Julien MERCIER
  • Publication number: 20250058449
    Abstract: The present disclosure is directed to kickback detection for devices, such as handheld drills. Kickback is detected using a gyroscope and an accelerometer, and is detected at the end of each of a plurality of time windows. At the end of each time window, kickback is detected based on, for example, a variance of a norm of gyroscope measurements. False kickback detections are then removed based on, for example, a minimum and a mean of accelerometer measurements. Kickback detection is completed before the next time window begins.
    Type: Application
    Filed: August 17, 2023
    Publication date: February 20, 2025
    Applicant: STMicroelectronics International N.V.
    Inventors: Mahesh CHOWDHARY, Krishna Chaitanya PALLE HAYAGREEVA
  • Publication number: 20250060466
    Abstract: A waveform generator includes a system control unit and signal channels controlled by the system control unit and configured to supply driving signals for driving a respective transducer of an array of transducers. Each signal channel includes a sequential access memory having rows, where each row contains an instruction word configured to generate a respective step of a waveform to be generated. A memory output of the sequential access memory is defined by an output row at a fixed location. The waveform to be generated is defined by a block of instruction words. Each signal channel also includes an internal control unit that is configured to sequentially move the content of the sequential access memory, based on the instruction word currently at the memory output, so that sequences of instruction words are provided at the output row.
    Type: Application
    Filed: November 7, 2024
    Publication date: February 20, 2025
    Applicant: STMicroelectronics S.r.l.
    Inventors: Stefano PASSI, Roberto Giorgio BARDELLI, Anna MORONI
  • Publication number: 20250063769
    Abstract: A transistor suited for use as an RF switch includes a semiconductor layer and a stack of a gate insulator layer and a conductive gate layer. A length of the conductive gate layer is smaller on the side of a lower surface, located in the vicinity of the gate insulator layer, and is greater on the side of an upper surface, opposite to the lower surface. Lateral sides of the conductive gate layer are covered, on a lower portion, with a first material and, on an upper portion, with a second material. The first material has a Young's modulus greater than a Young's modulus of the second material.
    Type: Application
    Filed: August 14, 2024
    Publication date: February 20, 2025
    Applicant: STMicroelectronics International N.V.
    Inventors: Siddhartha DHAR, Stephane MONFRAY
  • Patent number: 12231102
    Abstract: An audio amplifier includes: a buck controller configured to control an output voltage at a first supply terminal, the output voltage selected from a set including a plurality of output voltages, where the output voltage takes a settling time to settle; a first audio bridge including: a class-AB driver stage coupled to the first supply terminal, and a delay insertion circuit configured to receive a processed digital stream and provide the processed digital stream to the class-AB driver stage a delay time after receiving the processed digital stream, where the delay time is based on the settling time; and an audio amplitude detector configured to detect a first peak amplitude in the first digital audio stream, where the buck controller is configured to select a lowest output voltage from the set that is higher than the first peak amplitude plus a headroom voltage.
    Type: Grant
    Filed: October 24, 2023
    Date of Patent: February 18, 2025
    Assignee: STMicroelectronics (Shenzhen) R&D Co. Ltd.
    Inventors: XiangSheng Li, Ru Feng Du
  • Patent number: 12232435
    Abstract: An integrated circuit includes a substrate with an active area, a first insulating layer, a second insulating layer, and a phase-change material. The integrated circuit further includes a heating element in an L-shape, with a long side in direct physical contact with the phase-change material and a short side in direct physical contact with a via. The heating element is surrounded by first, second, and third insulating spacers, with the first insulating spacer having a planar first sidewall in contact with the long side of the heating element, a convex second sidewall, and a planar bottom face in contact with the short side of the heating element. The second and third insulating spacers are in direct contact with the first insulating spacer and the long side of the heating element.
    Type: Grant
    Filed: April 3, 2023
    Date of Patent: February 18, 2025
    Assignees: STMicroelectronics (Crolles 2) SAS, STMicroelectronics (Grenoble 2) SAS, STMicroelectronics (Rousset) SAS
    Inventors: Franck Arnaud, David Galpin, Stephane Zoll, Olivier Hinsinger, Laurent Favennec, Jean-Pierre Oddou, Lucile Broussous, Philippe Boivin, Olivier Weber, Philippe Brun, Pierre Morin
  • Patent number: 12230619
    Abstract: The present disclosure is directed to embodiments of optical sensor packages. For example, at least one embodiment of an optical sensor package includes a light-emitting die, a light-receiving die, and an interconnect substrate within a first resin. A first transparent portion is positioned on the light-emitting die and the interconnect substrate, and a second transparent portion is positioned on the light-receiving die and the interconnect substrate. A second resin is on the first resin, the interconnect substrate, and the first and second transparent portions, respectively. The second resin partially covers respective surfaces of the first and second transparent portions, respectively, such that the respective surfaces are exposed from the second resin.
    Type: Grant
    Filed: April 6, 2022
    Date of Patent: February 18, 2025
    Assignee: STMICROELECTRONICS PTE LTD
    Inventor: Jing-En Luan
  • Patent number: 12230565
    Abstract: A semiconductor region includes an isolating region which delimits a working area of the semiconductor region. A trench is located in the working area and further extends into the isolating region. The trench is filled by an electrically conductive central portion that is insulated from the working area by an isolating enclosure. A cover region is positioned to cover at least a first part of the filled trench, wherein the first part is located in the working area. A dielectric layer is in contact with the filled trench. A metal silicide layer is located at least on the electrically conductive central portion of a second part of the filled trench, wherein the second part is not covered by the cover region.
    Type: Grant
    Filed: February 9, 2024
    Date of Patent: February 18, 2025
    Assignee: STMicroelectronics (Rousset) SAS
    Inventor: Abderrezak Marzaki
  • Patent number: 12230602
    Abstract: A method for manufacturing electronic chips includes depositing, on a side of an upper face of a semiconductor substrate, in and on which a plurality of integrated circuits has been formed, a protective resin. The method includes forming, in the protective resin, at least one cavity per integrated circuit, in contact with an upper face of the integrated circuit. Metal connection pillars are formed by filling the cavities with metal. The integrated circuits are separated into individual chips by cutting the protective resin along cut lines extending between the metal connection pillars.
    Type: Grant
    Filed: July 8, 2022
    Date of Patent: February 18, 2025
    Assignee: STMICROELECTRONICS (TOURS) SAS
    Inventors: Ludovic Fallourd, Christophe Serre
  • Patent number: 12229370
    Abstract: A method of operating a display includes performing a non-synchronized touch scan pattern on a display with a controller coupled to the display. The non-synchronized touch scan pattern schedules touch scans independent of a refresh rate of the display. Upon the controller detecting a first synchronization pulse from a display controller coupled to the controller and the display, a first pulse-checking timer is started. Upon detecting a second synchronization pulse from the display controller and before the first pulse-checking timer expires, a first display refresh rate for the display is obtained from an interval between the first synchronization pulse and the second synchronization pulse. A synchronized touch scan pattern is performed with the controller, and is scheduled to avoid touch scans coinciding with refreshes of the display performed at the first display refresh rate.
    Type: Grant
    Filed: August 31, 2023
    Date of Patent: February 18, 2025
    Assignees: STMICROELECTRONICS LTD., STMICROELECTRONICS (BEIJING) R&D CO., LTD
    Inventors: Pengcheng Wen, Yuan Yun Wang
  • Patent number: 12230628
    Abstract: The present disclosure concerns a switching device comprising a first phosphorus-doped silicon layer on top of and in contact with a second arsenic-doped silicon layer. The present disclosure also concerns a method of making a switching device that includes forming a phosphorus-doped silicon layer in an arsenic-doped silicon layer.
    Type: Grant
    Filed: November 8, 2022
    Date of Patent: February 18, 2025
    Assignee: STMICROELECTRONICS (TOURS) SAS
    Inventor: Aurelie Arnaud
  • Patent number: 12230555
    Abstract: A power device for surface mounting has a leadframe including a die-attach support and at least one first lead and one second lead. A die, of semiconductor material, is bonded to the die-attach support, and a package, of insulating material and parallelepipedal shape, surrounds the die and at least in part the die-attach support and has a package height. The first and second leads have outer portions extending outside the package, from two opposite lateral surfaces of the package. The outer portions of the leads have lead heights greater than the package height, extend throughout the height of the package, and have respective portions projecting from the first base.
    Type: Grant
    Filed: December 22, 2023
    Date of Patent: February 18, 2025
    Assignee: STMICROELECTRONICS S.r.l.
    Inventors: Cristiano Gianluca Stella, Fabio Vito Coppone, Francesco Salamone
  • Patent number: 12229253
    Abstract: A system on a chip comprising a set of one-time programmable memory elements that comprises a first valid configuration; a second valid configuration; and a plurality of invalid configurations. The system on a chip also comprises a programming indicator initially comprising a first value and configured to be permanently set to a second value. The system on a chip further comprises a decoder circuit in communication with the set of one-time programmable memory elements to determine whether the set of one-time programmable memory elements is in the first valid configuration, the second valid configuration, or any one of the plurality of invalid configurations. The decoder circuit generates a threat-detection signal when the set of one-time programmable memory elements is in any of the plurality of invalid configurations when the programming indicator is permanently set to the second value.
    Type: Grant
    Filed: June 7, 2021
    Date of Patent: February 18, 2025
    Assignees: STMicroelectronics International N.V., STMicroelectronics (Alps) SAS
    Inventors: Asif Rashid Zargar, Gilles Eyzat, Charul Jain
  • Patent number: 12226909
    Abstract: A robotic device including one or more proximity sensing systems coupled to various portions of a robot body. The proximity sensing systems detect a distance of an object about the robot body and the robotic device reacts based on the detected distance. The proximity sensing systems obtain a three-dimensional (3D) profile of the object to determine a category of the object. The distance of the object is detected multiple times in a sequence to determine a movement path of the object.
    Type: Grant
    Filed: August 9, 2022
    Date of Patent: February 18, 2025
    Assignee: STMICROELECTRONICS, INC.
    Inventors: Cheng Peng, Xiaoyong Yang
  • Patent number: 12229063
    Abstract: In an embodiment, a system includes a contactless reader and an apparatus. The apparatus includes a contactless transponder including a contactless interface and a transponder wired interface and being configured to communicate with a contactless reader according to a contactless protocol through the contactless interface. The apparatus includes a bus coupled to the transponder wired interface, and at least one module coupled to the bus, the at least one module including a processing circuit, the contactless reader being configured to communicate instructions of a software program executable by the processing circuit to the at least one module through the contactless transponder.
    Type: Grant
    Filed: March 10, 2023
    Date of Patent: February 18, 2025
    Assignee: STMicroelectronics (Grenoble 2) SAS
    Inventor: Jean-Louis Labyre
  • Patent number: 12230357
    Abstract: The present description concerns an electronic device including: a first input configured to receive a clock signal, coupled by a first input buffer to a first circuit; and at least an output coupled by an output buffer to the first circuit, the output buffer being synchronized on first edges of the clock signal, wherein the first input buffer includes a data input coupled to the first input and is configured to maintain the value on its output constant whatever the value on its data input during a duration following each first edge of the clock signal.
    Type: Grant
    Filed: September 2, 2022
    Date of Patent: February 18, 2025
    Assignee: STMicroelectronics (Rousset) SAS
    Inventors: Francesco La Rosa, Thierry Giovinazzi