Abstract: Memory devices and methods of manufacturing such devices are provided herein. In at least one embodiment, a memory device includes a plurality of phase-change memory cells. An electrically-insulating layer covers lateral walls of each of the phase-change memory cells, and a thermally-insulating material is disposed on the electrically-insulating layer and covers the lateral walls of the phase-change memory cells.

Abstract: A memory circuit includes an array of memory cells arranged with first word lines connected to a first sub-array storing less significant bits of data and second word lines connected to a second sub-array storing more significant bits of data. A first word line signal is applied to a selected one of the first word lines to read less significant bits from the first sub-array, and a mathematical operation is performed on the read less significant bits to produce modified less significant bits that are written back to the first sub-array. If the read less significant bits are saturated, a second word line signal is applied to a selected one of the second word lines to read more significant bits from the second sub-array, and a mathematical operation is performed on the read more significant bits to produce modified more significant bits that are written back to the second sub-array.

Abstract: Methods and structures for forming strained-channel finFETs are described. Fin structures for finFETs may be formed in two epitaxial layers that are grown over a bulk substrate. A first thin epitaxial layer may be cut and used to impart strain to an adjacent channel region of the finFET via elastic relaxation. The structures exhibit a preferred design range for increasing induced strain and uniformity of the strain over the fin height.

Abstract: A method of manufacturing semiconductor devices, such as QFN/BGA flip-chip type packages, arranging on a leadframe one or more semiconductor chips or dice having a first side facing towards the leadframe and electrically coupled therewith and a second side facing away from the leadframe. The method also includes molding an encapsulation on the semiconductor chip(s) arranged on the leadframe, where the encapsulation has an outer surface opposite the leadframe and comprises laser direct structuring (LDS) material. Laser direct structuring processing is applied to the LDS material of the encapsulation to provide metal vias between the outer surface of the encapsulation and the second side of the semiconductor chip(s) and as well as a metal pad at the outer surface of the encapsulation.

Abstract: A system on a chip including a first-port controller for a first development port configured to receive a first development tool and a second-port controller for a second development port configured to receive a second development tool. The system on a chip further including a central controller in communication with the first-port controller, the second-port controller, and a security subsystem. The central controller being configured to manage authentication exchanges between the security subsystem and the first development tool and authentication exchanges between the security subsystem and the second development tool.

Abstract: A flash analog-to-digital converter (ADC) receives an input control signal and performs coarse tuning of a frequency of an output signal, produced between first and second nodes having an inductance coupled therebetween. The flash ADC quantizes an operating frequency range for the output signal produced between the first and second nodes as M·?f, where M is an integer from 0 to N?1, where N is a number of intervals into which a frequency range for the output signal is divided, and where ?f is a resulting frequency step produced by the quantizing. The value of M is generated based upon the input control signal and a word controlling switches of a plurality of switched capacitance circuits associated with the first and second nodes to close ones of those switches associated with the control word to coarsely tune the frequency of the output signal.

Abstract: An embodiment of the present disclosure relates to a method of detection of a touch contact by a sensor including a first step of comparison of a voltage with a first voltage threshold; and a second step of comparison of the voltage with a second voltage threshold, the second step being implemented if the first voltage threshold has been reached within a duration shorter than a first duration threshold, the second voltage threshold being higher than the first voltage threshold.

Abstract: A semiconductor device, such as a Quad-Flat No-lead (QFN) package, includes a semiconductor chip arranged on a die pad of a leadframe. The leadframe has an array of electrically-conductive leads around the die pad. The leads in the array have distal ends facing away from the die pad as well as recessed portions at an upper surface of the leads. Resilient material, such as low elasticity modulus material, is present at the upper surface of the leads and filling the recessed portions. An insulating encapsulation is molded onto the semiconductor chip. The resilient material is sandwiched between the insulating encapsulation and the distal ends of the leads. This resilient material facilitates flexibility of the leads, making them suited for reliable soldering to an insulated metal substrate.

Abstract: In accordance with an embodiment, a power supply circuit includes: a first transistor device comprising a first gate associated with a first transconductance and a second gate associated with a transconductance greater than the first transconductance; and a second transistor device including a third gate associated with a second transconductance and a fourth gate associated with a transconductance greater than the second transconductance. The second transistor device is configured to supply power to at least one load, the first and the third gates are controlled by a closed regulation loop, and the second and the fourth gates are controlled by a sampled reference voltage.

Abstract: A driving circuit for controlling a MEMS oscillator includes a digital conversion stage to acquire a differential sensing signal indicative of a displacement of a movable mass of the MEMS oscillator, and to convert the differential sensing signal of analog type into a digital differential signal of digital type. Processing circuitry is configured to generate a digital control signal of digital type as a function of the comparison between the digital differential signal and a differential reference signal indicative of a target amplitude of oscillation of the movable mass which causes the resonance of the MEMS oscillator. An analog conversion stage includes a ?? DAC and is configured to convert the digital control signal into a PDM control signal of analog type. A filtering stage of low-pass type, by filtering the PDM control signal, generates a control signal for controlling the amplitude of oscillation of the movable mass.

Abstract: A level-shifter circuit receives one or more input signals in an input level domain and includes provides at an output node an output signal in an output level domain shifted with respect to the input level domain. The circuit includes output circuitry including a first drive node and a second drive node that receive first and second logical signals so that the output signal has a first output level or a second output level in the output level domain as a function of at least one of the first and second logical signals. The circuit includes first and second shift capacitors coupled to the first and second drive nodes as well as capacitor refresh circuitry.

Abstract: A sensor includes detection circuitry and control circuitry coupled to the detection circuitry. The detection circuitry generates a detection signal indicative of a detected physical quantity. The control circuitry, in operation receives the detection signal and a frequency-indication signal, and generates a trigger signal based on the frequency-indication signal and a set of local reference signals. The sensor generates a digital output signal and a locking signal based on the trigger signal and the detection signal. The generating the digital output signal includes outputting a sample of the digital output signal based on the trigger signal. The locking signal is temporally aligned with the digital output signal.

Abstract: An in-memory computation (IMC) circuit includes a memory array formed by memory cells arranged in row-by-column matrix. Computational weights for an IMC operation are stored in the memory cells. Each column includes a bit line connected to the memory cells. A switching circuit is connected between each bit line and a corresponding column output. The switching circuit is controlled to turn on to generate the analog signal dependent on the computational weight and for a time duration controlled by the coefficient data signal. A column combining circuit combines (by addition and/or subtraction) and integrates analog signals at the column outputs of the biasing circuits. The addition/subtraction is dependent on one or more a sign of the coefficient data and a sign of the computational weight and may further implement a binary weighting function.

Abstract: A MEMS actuator includes a mobile mass suspended over a substrate in a first direction and extending in a plane that defines a second direction and a third direction perpendicular thereto. Elastic elements arranged between the substrate and the mobile mass have a first compliance in a direction parallel to the first direction that is lower than a second compliance in a direction parallel to the second direction. Piezoelectric actuation structures have a portion fixed with respect to the substrate and a portion that deforms in the first direction in response to an actuation voltage. Movement-transformation structures coupled to the piezoelectric actuation structures include an elastic movement-conversion structure arranged between the piezoelectric actuation structures and the mobile mass. The elastic movement-conversion structure is compliant in a plane formed by the first and second directions and has first and second principal axes of inertia transverse to the first and second directions.

Abstract: A method for determining temperature of a chip, includes generating a first voltage and a second voltage using a pair of bipolar-junction transistors, and generating a third voltage using another bipolar-junction transistor. When a most recent bit of a bitstream is a logic-zero, the difference between the first and second voltages is sampled using a switched-capacitor input-sampling circuit, and a difference between the first and second voltages is integrated, to produce a proportional-to-absolute-temperature voltage. The proportional-to-absolute-temperature voltage is quantized to produce a next bit of the bitstream. When the most recent bit of the bitstream is a logic-one, the third voltage is sampled using the switched-capacitor input-sampling circuit, and the third voltage is integrated, to produce a complementary-to-absolute-temperature voltage. The complementary-to-absolute-temperature voltage is quantized to produce a next bit of the bitstream.

Abstract: Generally described, one or more embodiments are directed to semiconductor packages comprising a plurality of leads and methods of forming same. The plurality of leads include active leads that are electrically coupled to bond pads of a semiconductor die and thereby coupled to active components of the semiconductor die, and inactive leads that are not electrically coupled to bond pads of the semiconductor die. The active leads have surfaces that are exposed at a lower surface of the semiconductor package and forms lands, while the inactive leads are not exposed at the lower surface of the package.

Abstract: A Low Voltage Differential Signaling (LVDS) transmitter includes driver circuit with a first transistor, a second transistor, a third transistor, a fourth transistor, a first resistor, and a second resistor. The first transistor is coupled between a first node and first output. The second transistor is coupled between the first node and a second output. The third transistor is coupled between the first output and a second node. The fourth transistor is coupled between the second output and the second node. The first resistor is coupled between the first output and a common mode node. The second resistor is coupled between the second output and the common mode node. A pre-driver circuit generates gate control signals controlling the first, second, third, and fourth transistors in response to a data signal. A controlled timing delay is applied to the timing of logic state transistors for the control signals.

Abstract: Single gate and dual gate FinFET devices suitable for use in an SRAM memory array have respective fins, source regions, and drain regions that are formed from portions of a single, contiguous layer on the semiconductor substrate, so that STI is unnecessary. Pairs of FinFETs can be configured as dependent-gate devices wherein adjacent channels are controlled by a common gate, or as independent-gate devices wherein one channel is controlled by two gates. Metal interconnects coupling a plurality of the FinFET devices are made of a same material as the gate electrodes. Such structural and material commonalities help to reduce costs of manufacturing high-density memory arrays.

Abstract: A device includes an interface, which, in operation, couples to a non-volatile memory. The device includes circuitry coupled to the interface. The circuitry, in operation: reads a data configuration structure stored on the non-volatile memory, the data configuration structure being associated with a client circuit of a plurality of client circuits; and configures the client circuit, the configuring including writing data words of the data configuration structure to the client circuit, the writing including determining an address of the client circuit, the address being associated with at least one of the data words, the determining being based on number of data words in the data configuration structure.

Abstract: A control circuit operates to control a switching stage of an electronic converter. The control circuit includes: first terminals providing drive signals to electronic switches of the switching stage; a second terminal receiving from a feedback circuit a first feedback signal proportional to a converter output voltage; and a third terminal configured to receive from a current sensor a second feedback signal proportional to an inductor current. A driver circuit provides the drive signals as a function of a PWM signal generated by a generator circuit as a function of the first and second feedback signals, a reference voltage and a slope compensation signal. A mode selection signal is generated as a function of a comparison between the input voltage and the output voltage. A feed-forward compensation circuit is configured to source and/or sink a compensation current as a function of a variation in the mode selection signal.