Abstract: An integrated circuit transistor device includes a semiconductor substrate providing a drain, a first doped region buried in the semiconductor substrate providing a body and a second doped region in the semiconductor substrate providing a source. A trench extends into the semiconductor substrate and passes through the first and second doped regions. An insulated polygate region within the trench surrounds a polyoxide region that may have void inclusion. The polygate region is formed by a first gate lobe and second gate lobe on opposite sides of the polyoxide region. A pair of gate contacts are provided at each trench. The pair of gate contacts includes: a first gate contact extending into the first gate lobe at a location laterally offset from the void and a second gate contact extending into the second gate lobe at a location laterally offset from the void.

Abstract: Merged-PiN-Schottky, MPS, device comprising: a substrate of SiC with a first conductivity; a drift layer of SiC with the first conductivity, on the substrate; an implanted region with a second conductivity, extending at a top surface of the drift layer to form a junction-barrier, JB, diode with the substrate; and a first electrical terminal in ohmic contact with the implanted region and in direct contact with the top surface to form a Schottky diode with the drift layer. The JB diode and the Schottky diode are alternated to each other along an axis: the JB diode has a minimum width parallel to the axis with a first value, and the Schottky diode has a maximum width parallel to the axis with a second value smaller than, or equal to, the first value. A breakdown voltage of the MPS device is greater than, or equal to, 115% of a maximum working voltage of the MPS device in an inhibition state.

Abstract: A method includes performing, by a terminal with an access card, a first relay attack check for the access card in accordance with a local value associated with the terminal and a local value associated with the access card; determining, by the terminal, that the access card has passed the first relay attack check, and based thereon, performing, by the terminal with the access card, an authentication check of the access card in accordance with the local value associated with the terminal, the local value associated with the access card, and a local challenge value associated with the terminal; and determining, by the terminal, that the access card has passed the first relay attack check and the authentication check, and based thereon, validating, by the terminal, the access card.

Abstract: The present disclosure relates to an image sensor that includes first and second pixels. One or more transistors of the first pixel share an active region with one or more transistors of the second pixel.

Abstract: An electronic device includes a modulator-demodulator circuit, a first integrated circuit for implementing a first subscriber module; and a second integrated circuit for implementing a second subscriber identification module. A data transmit-receive terminal of the first integrated circuit and a data transmit-receive terminal of the second integrated circuit are connected to a data transmit-receive terminal of the modulator-demodulator circuit. Reset terminals of the modulator-demodulator circuit and the first integrated circuit are connected so that the modulator-demodulator circuit can control deactivation of the first integrated circuit. A reset terminal of the second integrated circuit and an input/output terminal of the first integrated circuit are connected so that the first integrated circuit can control deactivation of the second integrated circuit.

Abstract: An in-memory computation device receives an input signal and provides an output signal. The device includes a memory array with memory cells coupled to word lines that receive word line activation signals indicative of the input signal and coupled to bit lines that generate bit line currents; and a digital detector for sampling the bit line current and, in response, providing the output signal. A digital detector includes: a control stage that compares the bit line current with at least one reference current and generates corresponding control signals; a selection stage that generates a total selection current based on the first bit line current and on the control signals; an integration stage that samples the total selection current; and a charge counter stage that generates the output signal on the basis of a sampled first total selection current and the control signals.

Abstract: An in-memory computation (IMC) system includes an in-memory computation circuit formed by a first phase change memory (PCM) array configured to store the computational weights for an in-memory computation operation. A data storage circuit is formed by a second PCM array configured to store backup data for the computational weights for the in-memory computation operation. The first PCM array includes PCM cells made of a phase change material provided by a first GST alloy, and the second PCM array includes PCM cells made of a phase change material provided by a second GST alloy different from the first GST alloy. A control circuit operates to read the backup data from the second PCM array and write to the first PCM array to refresh the computational weights for the in-memory computation operation from the backup data.

Abstract: A MEMS (MicroElectroMechanical System) device includes: a supporting body; a movable mass, constrained to the supporting body by flexures so as to be able to oscillate in a main direction; an actuator device, configured to apply to the movable mass an electrostatic actuation force, transverse to the main direction; and a control circuit configured to detect stiction conditions, in which the movable mass is stuck to the supporting body by a stiction force, and for driving the actuator device in response to recognition of the stiction conditions. The actuation force is a variable force with an actuation frequency band containing at least one resonance frequency in a direction transverse to the main direction of a mechanical system comprising the movable mass stuck to the supporting body.

Abstract: First signal processing is applied to a first input signal oscillating at an input frequency and a first set of control signals to generate a first output signal oscillating at a multiple of the input frequency with an amplitude controlled by a control signal in the first set of control signals. Second signal processing is applied to a second input signal oscillating in quadrature at the input frequency and a second set of control signals to generate a second output signal that oscillates at the multiple of the input frequency with an amplitude controlled by a control signal in the second set of control signals. A further output signal, generated in response to the first and second output signals, oscillates at the multiple of the input frequency with a phase shift controlled by a ratio of control signal amplitudes for the first and second sets of control signals.

Abstract: An integrated circuit package includes an integrated circuit die. The integrated circuit die includes core circuitry implemented in one or more layers of semiconductor material, a first cluster of first contact pads formed of a top metal layer of the integrated circuit die and coupled to the core circuitry, a second cluster of second contact pads formed of the top metal layer and coupled to the core circuitry, a first ESD protection line formed of the top metal layer extending between an area of the first cluster and an area of the second cluster, and ESD protection circuitry in the one or more layers of semiconductor material coupling each of the first contact pads and each of the second contact pads to the first ESD protection line by ESD protection circuitry. The integrated circuit package includes a passivation layer on the integrated circuit die and a second ESD protection line on the passivation layer formed of a redistribution metal layer and shorting a portion of the first ESD protection line.

Abstract: A multiplexer includes an input, an output, and a main switch configured to pass a signal from the input to the output. The multiplexer includes two bootstrap circuits that collectively maintain a constant voltage between terminals of the main switch during alternating phases.

Abstract: A system including an asynchronous finite state machine that transitions from a first state to a second state in response to receiving a virtual-clock event signal. The system further includes a trigger circuit that asserts a trigger signal when a first-state asynchronous event signal is asserted while the asynchronous finite state machine is in the first state. The system further including a virtual clock-pulse circuit configured to generate the virtual-clock event signal after receiving the trigger signal.

Abstract: An HEMT transistor includes a semiconductor body having a semiconductive heterostructure. A gate region, of conductive material, is arranged above and in contact with the semiconductor body. A first insulating layer extends over the semiconductor body, laterally to the conductive gate region. A second insulating layer extends over the first insulating layer and the gate region. A first field plate region, of conductive material, extends between the first and the second insulating layers, laterally spaced from the conductive gate region along a first direction. A second field plate region, of conductive material, extends over the second insulating layer, and the second field plate region overlies and is vertically aligned with the first field plate region.

Abstract: In an embodiment a control device includes a first input configured to receive a measurement signal representative of an output voltage of a switching circuit of a voltage regulator, a state determination block coupled to the first input and configured to generate a signal of actual operating condition of the voltage regulator and a driving signals generation module configured to generate at least one switching command signal for the switching circuit from an error signal representative of a difference between the output voltage and a nominal voltage, wherein the driving signals generation module includes an error-compensation circuit having a transfer function and configured to generate a control signal from the error signal and the actual operating condition signal, the control signal being a function of the actual operating condition.

Abstract: A method of testing a photonic device includes providing a plurality of optical test signals at respective inputs of a first plurality of inputs of an optical input circuit located on a substrate, combining the plurality of optical test signals into a combined optical test signal at an output of the optical input circuit, transmitting the combined optical test signal through the output to an input waveguide of an optical device under test, the optical device under test being located on the substrate, and measuring a response of the optical device under test to the combined optical test signal. Each of the plurality of optical test signals comprises a respective dominant wavelength of a plurality of dominant wavelengths.

Abstract: In accordance with an embodiment, a system includes a phase-locked loop (PLL) configured to provide a first local oscillator (LO) signal and a voltage-controlled oscillator (VCO) signal; a first quadrature demodulator configured to downconvert global navigation satellite system signals to produce a first intermediate frequency (IF) signal; a first signal processing chain configured to pass the first IF signal; a second signal processing chain comprising a first frequency divider configured to produce a second LO signal based on the first LO signal, and a second quadrature demodulator configured to convert the first IF signal to a second IF signal using the second LO signal; and a third signal processing chain comprising a second frequency divider configured to produce a third LO signal based on the VCO signal, and a third quadrature demodulator configured to convert the first IF signal to a third IF signal using the third LO signal.

Abstract: The present description concerns a package for an electronic device. The package including a plate and a lateral wall, separated by a layer made of a bonding material and at least one region made of a material configured to form in the region an opening between the inside and the outside of the package when the package is heated.

Abstract: Embedded systems and methods of reading or writing data or instructions of at least one application in a non-volatile memory are disclosed. A method includes reading or writing data or instructions of at least one application in a non-volatile memory of an embedded system. The data or instructions transit through a memory area and are interpreted by a distinct program of an operating system of the embedded system.

Abstract: A control circuit and method, wherein an error signal is generated representative of a difference between an output voltage of a switching circuit and a nominal signal; a single control signal is generated, representative of an average error of the error signal; the single control signal is compared with a first periodic reference signal and a second periodic reference signal; a first pulse width modulated signal is generated by a Buck modulator; and a second pulse width modulated signal is generated by a Boost modulator. The maximum value of the first periodic reference signal and the minimum value of the second periodic reference signal are higher and lower, respectively, than the single control signal in a transient control mode between a Buck control mode and a Boost control mode.

Abstract: An image acquisition device includes an array of color filters and an array of microlenses over the array of color filters. At least one layer made from an inorganic dielectric material is formed between the array of color filters and the array of microlenses.