Abstract: A device includes a semiconductor substrate. A step is formed at a periphery of the semiconductor substrate. A first layer, made of polysilicon doped in oxygen, is deposited on top of and in contact with a first surface of the substrate. This first layer extends at least on a wall and bottom of the step. A second layer, made of glass, is deposited on top of the first layer and the edges of the first layer. The second layer forms a boss between the step and a central area of the device.

Abstract: At least one semiconductor chip or die is held within at a chip retaining formation provided in a chip holding device. The chip holding device is then positioned with the at least one semiconductor chip or die arranged facing a chip attachment location in a chip mounting substrate. This positioning produces a cavity between the at least one semiconductor chip or die arranged at the chip retaining formation and the chip attachment location in the chip mounting substrate. A chip attachment material is dispensed into the cavity. Once cured, the chip attachment material attaches the at least one semiconductor chip or die onto the substrate at the chip attachment location in the chip mounting substrate.

Abstract: The present disclosure is directed to lift-up gesture detection for electronic devices. An initial lift-up gesture is detected in response to an orientation change and a lift-up motion of the device being detected. The initial lift-up gesture is validated as a true lift-up gesture in a case where a shaking motion of the device is not being detected when the initial lift-up gesture is detected. If a shaking motion of the device is detected when the initial lift-up gesture is detected, the initial lift-up gesture is rejected.

Abstract: A method for transmission of monochrome video data of a monochromatic image, wherein three different source monochromatic pixels are encoded by a transmitting device into one compressed three-color pixel; the compressed three-color pixel are transmitted by the transmitting device. The transmitted compressed three-color pixel are received at a receiving device; and the compressed three-color pixel decoding are decoded by the receiving device into three different sink monochromatic pixels. The transmitting device acquires the three different source monochromatic pixels, extracts a single-color value from each of the three different source monochromatic pixels, and generates the compressed three-color pixel using the single-color values extracted from the three different source monochromatic pixels.

Abstract: A memory system includes a memory with memory blocks. A first logic circuit performs an XOR combinational logic function of a current value of a data addressing mode and of at least one bit of a first data packet including an error correction code of a data element to be written. A second data packet, generated by the first logic circuit, is stored into one of the memory blocks. A second logic circuit performs an XOR combinational logic function of at least one bit of the second packet (such as read from one of the memory blocks) and of the current value of the addressing mode. A weight of the bit of the first data packet corresponds to a weight of the at least one bit of the second read data packet.

Abstract: A circuit includes a first capacitance array formed by n nominally equal capacitive elements. A first electrode of each capacitive element is coupled, via respective switches to either a reference voltage or ground. A differential amplifier has a first input coupled to an output of a first capacitance array, a second input grounded, and an output generating a voltage ramp. A capacitive feedback circuit couples the output of the differential amplifier to the first input. A second capacitance array has an output coupled to the first input of the differential amplifier. The capacitive elements of the first capacitance array are organized in sets. The circuit operates by controllably coupling, set by set, second electrodes of the capacitive elements of the first capacitance array to the first input of the differential amplifier.

Abstract: A method of corrupting contents of a memory array includes asserting a signal at a reset node to thereby cause starving of current supply to the memory array, and selecting bit lines and complementary bit lines associated with desired columns of the memory array that contain memory cells to have their contents corrupted. For each desired column, a logic state of its bit line and complementary bit line are forced to a same logic state. Each word line associated with desired rows of the memory array that contains memory cells to have their contents corrupted is simultaneously asserted, and then simultaneously deasserted to thereby place each memory cell to have its contents corrupted into a metastable state during a single clock cycle.

Abstract: A device includes an array powered between virtual supply and reference voltages, with each row having a wordline and each column having a bitline and complementary bitline. The virtual supply voltage circuit includes a first transistor configured to output the virtual supply voltage, and a second transistor configured to turn off to reduce current supplied to the array. A column driver, while the second transistor is off, drives the bitlines and complementary bitlines to opposite logic states in response to an internal clock. A row decoder asserts wordlines in response to the internal clock. Due to the reduced current supplied to the array, the bitlines remain at a logic high state and the complementary bitlines fall to a logic-low state, resetting the memory cells.

Abstract: The present disclosure is directed to an integrated circuit that includes a non-volatile memory (NVM). The integrated circuit includes a bias generator that produces stable wordline and bitline voltages for a reliable read operation of the NVM. This disclosure is directed to low voltage memory operations of memory read, erase verify, and program verify. The present disclosure is directed to non-volatile memory circuits that can also operate at low supply voltages in digital voltage supply range.

Abstract: A microelectromechanical device includes a fixed structure having a frame defining a cavity, a tiltable structure elastically suspended above the cavity with main extension in a horizontal plane, a piezoelectrically driven actuation structure which can be biased to cause a desired rotation of the tiltable structure about a first and second rotation axes, and a supporting structure integral with the fixed structure and extending in the cavity starting from the frame. Lever elements are elastically coupled to the tiltable structure at a first end by elastic suspension elements and to the supporting structure at a second end by elastic connecting elements which define a lever rotation axis. The lever elements are elastically coupled to the actuation structure so that their biasing causes the desired rotation of the tiltable structure about the first and second rotation axes.

Abstract: A method includes receiving, at a master agent, announcements from candidate consumer agents indicating the presence of the candidate consumer agents. Each announcement includes display parameters for a display of the corresponding candidate consumer agent. The method further includes receiving at the master agent content parameters from a producer agent, the content parameters defining characteristics of content to be provided by the consumer agent. A mosaic screen is configured based on the received announcements and the content parameters. This configuring of the mosaic screen includes selecting ones of the consumer agents for which an announcement was received and generating content distribution parameters based on the content parameters and the display parameters of the selected ones of the consumer agents. The generated content distribution parameters are provided to the consumer agent.

Abstract: First combinational, arithmetic, or combinational and arithmetic, operations are applied to data and an expected value, generating result bit sequences. When the value of the data corresponds to the expected value, the result bit sequences are different from each other and correspond to expected values of the result bit sequences. Second operations are applied a first memory address, a second memory address, and the result bit sequences, generating a memory address. When values of the generated result bit sequences correspond to the expected values of the result bit sequences, the generated memory address corresponds to the first memory address. When values of the generated plurality of result bit sequences do not correspond to the expected values of the result bit sequences, the generated memory address corresponds to the second memory address. A software routine starting at the generated memory address is executed.

Abstract: An example gesture detection method includes detecting at a first time a first touch on a touch panel, where the first touch covers a first area of the touch panel, and then determining whether the first touch is within a track region that surrounds a fingerprint sensing region. The method includes determining whether the first touch is within the fingerprint sensing region, the fingerprint sensing region including a sensing surface of a fingerprint sensor. The method includes determining a first fraction of the fingerprint sensing region covered by the first touch and determining whether the first fraction exceeds a first threshold. The first threshold is a majority of the fingerprint sensing region. The method includes determining a second fraction of all of the first area that is within the fingerprint sensing region and determining whether the second fraction exceeds a second threshold, where the second threshold is a fraction indicative of a majority of an area associated with the corresponding touch.

Abstract: A piezoelectric microelectromechanical structure is provided with a piezoelectric stack having a main extension in a horizontal plane and a variable section in a plane transverse to the horizontal plane. The stack is formed by a bottom-electrode region, a piezoelectric material region arranged on the bottom-electrode region, and a top-electrode region arranged on the piezoelectric material region. The piezoelectric material region has, as a result of the variable section, a first thickness along a vertical axis transverse to the horizontal plane at a first area, and a second thickness along the same vertical axis at a second area. The second thickness is smaller than the first thickness. The structure at the first and second areas can form piezoelectric detector and a piezoelectric actuator, respectively.

Abstract: In various embodiments, the present disclosure provides semiconductor devices, packages, and methods. In one embodiment, a device includes a die pad, a lead that is spaced apart from the die pad, and an encapsulant on the die pad and the lead. A plurality of cavities extends into at least one of the die pad or the lead to a depth from a surface of the at least one of the die pad or the lead. The depth is within a range from 0.5 ?m to 5 ?m. The encapsulant extends into the plurality of cavities. The cavities facilitate improved adhesion between the die pad or lead and the encapsulant, as the cavities increase a surface area of contact with the encapsulant, and further increase a mechanical interlock with the encapsulant, as the cavities may have a rounded or semi-spherical shape.

Abstract: A low power crystal oscillator circuit having a high power part and a low power part. Oscillation is initialized using the high power part. Once the crystal is under stable oscillation, the circuit switches to the low power part and continue operation for a long duration.

Abstract: The system on a chip includes at least a first digital domain configured to be reinitialized by a first reinitialization signal, a second digital domain and an interface circuit. The interface circuit includes a starting register in the first digital domain, a destination register in the second digital domain and a synchronization circuit in the first digital domain. The interface circuit is configured to transfer data from the starting register to the destination register upon command of a control signal transmitted by the synchronization circuit. The starting register and the synchronization circuit are configured to not be reinitialized by the first reinitialization signal.

Abstract: A satellite tracking channel has a frequency loop tracking a carrier frequency of a satellite signal. A first indication of a spoofed signals is generated based on a determined satellite signal noise floor value associated with the satellite tracking channel and a tracking channel signal noise threshold associated with the satellite tracking channel. A second indication of a spoofed signal is generated based on a determining satellite tracking phase noise associated with the satellite tracking channel and a tracking channel phase noise threshold associated with the satellite tracking channel. Reception of a spoofed signal on the satellite tracking channel is detected based on the generated first indication of a spoofed signal and the generated second indication of the spoofed signal.

Abstract: A circuit includes frequency multiplier circuitry having input nodes configured to receive an input signal and an anti-phase version thereof, the input signal having a first frequency value, wherein the frequency multiplier circuitry is configured to produce a current signal at a second frequency value that is an even multiple of the first frequency value and a transformer including a primary side and a secondary side, wherein the primary side comprises a primary inductance coupled to the frequency multiplier circuitry to receive the current signal therefrom, wherein the secondary side is configured to provide a frequency multiplied voltage signal, and wherein the frequency multiplier circuitry and the transformer are cascaded between at least one first node and a second node, the at least one first node and the second node couplable to a supply node and ground.

Abstract: A Junction Barrier Schottky device includes a semiconductor body of SiC having a first conductivity. An implanted region having a second conductivity, extends into the semiconductor body from a top surface of the semiconductor body to form a junction barrier diode with the semiconductor body. An electrical terminal is in ohmic contact with the implanted region and in direct electrical contact with the top surface, laterally to the implanted region, to form a Schottky diode with the semiconductor body. The implanted region is formed by a first and a second portion electrically connected directly to each other and aligned along an alignment axis transverse to the top surface. Orthogonally to the alignment axis, the first portion has a first maximum width and the second portion has a second maximum width greater than the first maximum width.