Patents Assigned to STMicroelectronics
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Publication number: 20240120838Abstract: In a DC-DC converter, a duty-cycle control signal is generated in response to comparing the switching stage output voltage and a reference voltage signal. A first circuit compares the duty-cycle control signal and a ramp to produce a PWM signal. A second circuit compares the duty-cycle control signal and a skip threshold to produce a skip control signal which halts switching operation of the switching stage. A count is made of number of periods of the skip control signal during a monitoring time window and the number of periods of a clock signal during a period of the skip control signal is counted. When the counted number of skip control signal periods is within a first range and the counted number of clock signal periods is within a second range, a common detection signal is asserted to trigger varying a value of the skip threshold signal.Type: ApplicationFiled: October 3, 2023Publication date: April 11, 2024Applicant: STMicroelectronics S.r.l.Inventors: Alessandro BERTOLINI, Alberto CATTANI, Alessandro GASPARINI
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Publication number: 20240120638Abstract: An electronic device includes a first layer with an antenna and a second metal layer that extends over the entire first layer. The second metal layer includes at least one laterally-closed cavity that is located vertically above the antenna. The cavity is filled, at least in part, by a resin material. A first plate supporting a second metal plate extends over the cavity with the second metal plate positioned vertically above the antenna. The first metal plate may be supported by a ledge within the cavity. Alternatively, the second metal plate is embedded in the resin filling the cavity, with the second metal plate positioned vertically above the antenna.Type: ApplicationFiled: December 19, 2023Publication date: April 11, 2024Applicant: STMicroelectronics (Alps) SASInventor: Deborah COGONI
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Patent number: 11954260Abstract: A system and method for determining handedness in a device. The system including a first electrode, a second electrode, a sensor, and a processing circuit coupled to each other. The first electrode is placed at a first location, and the second electrode is placed at a second location on the device—the first location is different from the second location. The electrodes are configured to sense a variation in an electrostatic field in response to a user interacting with the device. The sensor detects a differential potential between the first electrode and the second electrode, and the processing circuit determines whether the user is interacting with the device using a left hand or a right hand. The determining is based on data received from the sensor corresponding to the differential potential.Type: GrantFiled: July 13, 2021Date of Patent: April 9, 2024Assignees: STMicroelectronics S.r.l., STMicroelectronics (Shenzhen) R&D Co. Ltd.Inventors: Mirko Guarnera, Wenbin Yang, Enrico Rosario Alessi, Fabio Passaniti
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Patent number: 11954922Abstract: A time series of face images of a human during a human activity are captured. A first artificial neural network (ANN) processing pipeline processes the captured time series of face images to provide a first attention level indicator signal. An electrophysiological signal indicative of the level of attention of the human during the activity is also captured. A second ANN processing pipeline processes the sensed electrophysiological signal to providing a second attention level indicator signal. A risk indicator signal is then generated based on at least one of the first attention level indicator and second attention level indicator. A user circuit is then triggered as a result of the risk indicator reaching or failing to reach at least one attention level threshold.Type: GrantFiled: April 7, 2022Date of Patent: April 9, 2024Assignee: STMicroelectronics S.r.l.Inventors: Francesco Rundo, Giancarlo Asnaghi, Sabrina Conoci
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Patent number: 11955481Abstract: A microelectronic device includes a PNP transistor and NPN transistor arranged vertically in a P-type doped semiconductor substrate. The PNP and NPN transistors are manufactured by: forming an N+ doped isolating well for the PNP transistor in the semiconductor substrate; forming a P+ doped region in the N+ doped isolating well; epitaxially growing a first semiconductor layer on the semiconductor substrate; forming an N+ doped well for the NPN transistor, where at least part of the N+ doped well extends into the first semiconductor layer; then epitaxially growing a second semiconductor layer on the first semiconductor layer; forming a P doped region forming the collector of the PNP transistor in the second semiconductor layer and in electrical contact with the P+ doped region; and forming an N doped region forming the collector of the NPN transistor in the second semiconductor layer and in electrical contact with the N+ doped well.Type: GrantFiled: November 22, 2022Date of Patent: April 9, 2024Assignee: STMicroelectronics (Crolles 2) SASInventor: Jean Jimenez Martinez
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Patent number: 11956324Abstract: An integrated circuit includes sensing circuitry and processing circuitry. The processing circuitry processes received sensor-session requests and received sensor-service requests. Processing a received sensor-service request includes determining a type of the received sensor-service request. In response to determining the received sensor-service request is of a first type, results information is generated in response to the received sensor-service request of the first type based on sensor data generated by the sensing circuitry. In response to determining the received sensor-service request is of a second type, remote-server processing based on the received sensor-service request of the second type is initiated, and a response to the received sensor-service request of the second type is generated based on a received response to the initiated remote-server processing.Type: GrantFiled: January 7, 2021Date of Patent: April 9, 2024Assignee: STMICROELECTRONICS S.r.l.Inventors: Enrico Rosario Alessi, Fabio Passaniti
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Patent number: 11956638Abstract: In an embodiment the method a includes performing, by an integrated circuit (IC) card hosted in a local equipment, authentication with a contactless subscriber device when the subscriber device is within a communication range of a contactless interface of the local equipment, receiving, by the IC card, an identifier (SID) identifying a software module from the subscriber device, the software module configured to enable a subscription profile for a mobile network operator, performing a checking operation at the IC card whether the SID matches a software module identifier stored in the IC card and selectively performing one of downloading the software module to the IC card, enabling the software module at the IC card or disabling the software module at the IC card as a result of performing the checking operation.Type: GrantFiled: September 30, 2021Date of Patent: April 9, 2024Assignee: STMicroelectronics S.r.l.Inventors: Marco Alfarano, Sofia Massascusa
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Patent number: 11950911Abstract: An embodiment method comprises collecting at least one electrophysiological signal of a human over a limited time duration, and computing a set of electrophysiological signal features. The computing comprises at least one of: providing at least one reference electrophysiological signal and applying dynamic time warping processing to the at least one collected and at least one reference electrophysiological signals, applying stacked-auto-encoder artificial neural network processing to the collected electrophysiological signal, or filtering the electrophysiological signal collected via joint low-pass and high-pass filtering. The method further comprises applying pattern recognition processing to the computed set of features, producing a virtual key signal indicative of an identity of the human, and applying the virtual key signal to a user circuit to switch it between a first state and a second state as a result of the virtual key signal matching an authorized key signal stored in the user circuit.Type: GrantFiled: September 1, 2020Date of Patent: April 9, 2024Assignee: STMicroelectronics S.r.l.Inventors: Francesco Rundo, Sabrina Conoci, Concetto Spampinato
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Patent number: 11953813Abstract: Disclosed herein is a microelectromechanical device that features a fixed structure defining a cavity, a tiltable structure elastically suspended within the cavity, and a piezoelectrically driven actuation structure that rotates the tiltable structure about a first rotation axis. The actuation structure includes driving arms with piezoelectric material, elastically coupled to the tiltable structure by decoupling elastic elements that are stiff to out-of-plane movements but compliant to torsional movements. The tiltable structure is elastically coupled to the fixed structure at the first rotation axis using elastic suspension elements, while the fixed structure forms a frame surrounding the cavity with supporting elements. A lever mechanism is coupled between a supporting element and a driving arm.Type: GrantFiled: April 14, 2023Date of Patent: April 9, 2024Assignee: STMicroelectronics S.r.l.Inventors: Nicolo' Boni, Roberto Carminati, Massimiliano Merli
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Patent number: 11954548Abstract: A connector that is configured to receive a smart card includes: a first contact configured to receive a power supply voltage and corresponding to a first (power supply) contact area of the smart card, a second contact configured to receive a reference voltage and corresponding to contact a second (reference voltage) contact area of the smart card, and a third contact corresponding to a three-state (input/output) contact area of the smart card. A first light-emitting diode having an anode coupled to the third contact and a cathode coupled to the second contact. A second light-emitting diode has a cathode coupled to the third contact and an anode coupled to the first contact. Turning on/off of the first and second light-emitting diode is controlled by the smart card through the signal at the three-state (input/output) contact area.Type: GrantFiled: November 5, 2021Date of Patent: April 9, 2024Assignees: STMicroelectronics (Grand Ouest) SAS, STMicroelectronics (Rousset) SASInventors: Frederic Gouabau, Olivier Rouy
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Patent number: 11955480Abstract: The present disclosure concerns an integrated circuit comprising a substrate, the substrate comprising a first region having a first thickness and a second region having a second thickness smaller than the first thickness, the circuit comprising a three-dimensional capacitor formed inside and on top of the first region, and at least first and second connection terminals formed on the second region, the first and second connection terminals being respectively connected to first and second electrodes of the three-dimensional capacitor.Type: GrantFiled: May 11, 2022Date of Patent: April 9, 2024Assignee: STMICROELECTRONICS (TOURS) SASInventor: Mohamed Boufnichel
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Patent number: 11954589Abstract: An artificial-neuron device includes an integration-generation circuit coupled between an input at which an input signal is received and an output at which an output signal is delivered, and a refractory circuit inhibiting the integrator circuit after the delivery of the output signal. The refractory circuit is formed by a first MOS transistor having a first conduction-terminal coupled to a supply node, a second conduction-terminal coupled to a common node, and a control-terminal coupled to the output, and a second MOS transistor having a first conduction-terminal coupled to the input, a second conduction-terminal coupled to a reference node at which a reference voltage is received, and a control-terminal coupled to the common node. A resistive-capacitive circuit is coupled between the supply node and the reference node and having a tap coupled to the common node, with the inhibition duration being dependent upon a time constant of the resistive-capacitive circuit.Type: GrantFiled: January 11, 2022Date of Patent: April 9, 2024Assignee: STMicroelectronics SAInventors: Philippe Galy, Thomas Bedecarrats
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Patent number: 11955877Abstract: A method to operate a DC-DC power converter in a low power burst mode, the method including sampling an output voltage of the DC-DC power converter with a sampling frequency to determine when to initiate a burst for the low power burst mode; and adapting the sampling frequency based on the output voltage.Type: GrantFiled: July 28, 2021Date of Patent: April 9, 2024Assignee: STMicroelectronics S.r.l.Inventors: Alessandro Nicolosi, Giovanni Sicurella
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Patent number: 11953515Abstract: A method of processing information of a rotating wheel includes measuring angular velocity of a rotating wheel with a gyroscopic sensor, determining an instantaneous position of the rotating wheel with an accelerometer, and determining the angular positions of the rotating wheel based on the measured angular velocity and the instantaneous position of the rotating wheel. The gyroscopic sensor and the accelerometer are mounted on the rotating wheel.Type: GrantFiled: February 17, 2022Date of Patent: April 9, 2024Assignee: STMicroelectronics (China) Investment Co., Ltd.Inventor: Daopeng Fu
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Patent number: 11953546Abstract: According to one aspect, an integrated circuit includes: an electronic module configured to generate a voltage at an output, and an electronic control circuit coupled to an output of the electronic module, the electronic control circuit comprising an emissive electronic component. The electronic control circuit is configured to cause the emissive electronic component to emit light radiation as a function of a value of the voltage at the output of the electronic module relative to a value of an operating voltage of the electronic module, and the operating voltage is specific thereto during normal operation of this electronic module. The light radiation emitted by the emissive electronic component is configured to diffuse to an outer face of the integrated circuit.Type: GrantFiled: March 9, 2023Date of Patent: April 9, 2024Assignees: STMicroelectronics (Alps) SAS, STMicroelectronics (Grenoble 2) SASInventors: Etienne Auvray, Tommaso Melis, Philippe Sirito-Olivier
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Patent number: 11957067Abstract: A memory cell includes a selection transistor having a control gate and a first conduction terminal connected to a variable-resistance element. The memory cell is formed in a wafer comprising a semiconductor substrate covered with a first insulating layer, the insulating layer being covered with an active layer made of a semiconductor. The gate is formed on the active layer and has a lateral flank covered with a second insulating layer. The variable-resistance element includes a first layer covering a lateral flank of the active layer in a trench formed through the active layer along the lateral flank of the gate and reaching the first insulating layer, and a second layer made of a variable-resistance material.Type: GrantFiled: May 24, 2021Date of Patent: April 9, 2024Assignees: STMICROELECTRONICS (CROLLES 2) SAS, STMICROELECTRONICS (ROUSSET) SASInventors: Philippe Boivin, Simon Jeannot
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Publication number: 20240113704Abstract: A method for controlling a MOS transistor compares a first voltage between a drain and a source of the MOS transistor to a second controllable threshold voltage. When the first voltage is smaller than a third voltage, a fourth control voltage is applied to the MOS transistor that is greater than a fifth threshold voltage of the MOS transistor. When the first voltage is greater than the second voltage, the fourth control voltage applied to the MOS transistor is smaller than the fifth voltage. The second voltage is equal to a first constant value between a first time and a second time, and is equal to a second variable value between the second time and a third time. The second value is equal to a sum of the first voltage and a sixth positive voltage. The third time corresponds to a time when the first voltage inverts.Type: ApplicationFiled: September 22, 2023Publication date: April 4, 2024Applicant: STMicroelectronics (Tours) SASInventors: Diawoye CISSE, Bertrand RIVET, Frederic GAUTIER
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Publication number: 20240112748Abstract: A memory circuit includes an address port, a data input port and a data output port. An upstream shadow logic circuit is coupled to provide address data to the address port of the memory circuit and input data to the data input port of the memory circuit. A downstream shadow logic circuit is coupled to receive output data from the data output port of the memory circuit. The memory circuit includes a bypass path between the address port and the data output port. This bypass path is activated during a testing operation to pass bits of the address data (forming test data) applied by upstream shadow logic circuit from the address port to the data output port.Type: ApplicationFiled: July 31, 2023Publication date: April 4, 2024Applicant: STMicroelectronics International N.V.Inventors: Tanuj KUMAR, Hitesh CHAWLA, Bhupender SINGH, Harsh RAWAT, Kedar Janardan DHORI, Manuj AYODHYAWASI, Nitin CHAWLA, Promod KUMAR
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Publication number: 20240112728Abstract: A memory array includes sub-arrays with memory cells arranged in a row-column matrix where each row includes a word line and each sub-array column includes a local bit line. A control circuit supports a first operating mode where only one word line in the memory array is actuated during memory access and a second operating mode where one word line per sub-array is simultaneously actuated during an in-memory computation performed as a function of weight data stored in the memory and applied feature data. Computation circuitry coupling each memory cell to the local bit line for each column of the sub-array logically combines a bit of feature data for the in-memory computation with a bit of weight data to generate a logical output on the local bit line which is charge shared with the global bit line.Type: ApplicationFiled: September 11, 2023Publication date: April 4, 2024Applicant: STMicroelectronics International N.V.Inventors: Harsh RAWAT, Kedar Janardan DHORI, Dipti ARYA, Promod KUMAR, Nitin CHAWLA, Manuj AYODHYAWASI
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Publication number: 20240113064Abstract: An electronic device includes an integrated circuit (IC) with its second face bonded to a first surface of a first support. A conductive clip has a first portion that is elongate and extends across the IC, having its second surface bonded to a first face of the IC by a solder layer. A second portion of the clip extends from the first portion away from the IC toward a second support with the second surface bonded to a first surface of the second support. A first surface of the clip has a pattern formed therein including a depressed floor with fins extending upwardly therefrom. Through-holes extend through the depressed floor to the second surface of the clip. An encapsulating layer covers portions of the first and second supports, IC, and clip while leaving the first surface of the first portion exposed to permit heat to radiate away therefrom.Type: ApplicationFiled: August 11, 2023Publication date: April 4, 2024Applicant: STMicroelectronics, Inc.Inventor: Jefferson Sismundo TALLEDO