Abstract: A pixel includes a first doped region of a first conductivity type and a second doped region of a second conductivity type. The first doped region includes first and second layers forming a heterojunction. A dopant concentration of the first layer is greater than a dopant concentration of the second layer. The first layer is made of a semiconductor material and the second layer includes quantum dots. The second doped region is in contact with the second layer, with the first layer being laterally surrounded by an insulated conductive wall that is biased to a negative voltage.

Abstract: Disclosed herein is a system for measuring current, including an input inductor and a self-test inductor through which respective input and self-test currents flow. A Hall-effect sensor circuit senses magnetic fields around these inductors, producing differential voltage outputs. These outputs are received by an input and self-test extraction circuit, which alternatingly outputs differential voltages representative of the magnetic fields around the inductors. Amplification of these differential voltages is performed by an amplifier. Sampling of the amplified differential voltages is performed by two sample/hold circuits, each designated for a specific inductor's magnetic field. An integrator circuit adjusts a voltage for the Hall effect sensor circuit, causing the gain applied to the sampled differential voltage to remain consistent and uninfluenced by the sensitivity of the Hall effect sensor circuit.

Abstract: A device includes trenches. The trenches each include a conductive element configured to electrically couple coupling fingers of transistor gates located on a first side of a first layer, to a second layer extending on the side of a second face of the first layer.

Abstract: The present disclosure is directed to a device with enhanced human activity recognition. The device detects a human activity using one more motion sensors, and enhances the detected human activity depending on whether the device is in an indoor environment or an outdoor environment. The device utilizes one or more electrostatic charge sensors to determine whether the device is in an indoor environment or an outdoor environment.

Abstract: An audio device includes a gain step selection circuit that receives a different requested gain value and an associated requested step size from each of a plurality of sources, compares each requested gain value to a same feedback gain value and generates a polarity based thereupon, performs step polarization on each requested step size as a function of the generated polarity therefor to thereby generate a plurality of step values, and outputs a least of the plurality of step values as an output step value. An accumulator circuit generates a current input gain value based upon the output step value and the feedback gain value, and then updates the feedback gain value to be equal to the current input gain value. A normalizing circuit multiplies an input data value by the current input gain value and applies a truncation function to a result thereof to produce an output data value.

Abstract: A vertical-conduction MOSFET device formed in a body of silicon carbide having a first and a second face and a peripheral zone. A drain region, of a first conductivity type, extends in the body between the two faces. A body region, of a second conductivity type, extends in the body from the first face, and a source region, having the first conductivity type, extends to the inside of the body region from the first face of the body. An insulated gate region extends on the first face of the body and comprises a gate conductive region. An annular connection region, of conductive material, is formed within a surface edge structure extending on the first face of the body, in the peripheral zone. The gate conductive region and the annular connection region are formed by a silicon layer and by a metal silicide layer overlying the silicon layer.

Abstract: An enhancement-mode high-electron-mobility transistor comprises a structure including a stack made of III-V semiconductor materials defining an interface and capable of forming a conduction layer in the form of a two-dimensional electron gas layer; a source electrode and a drain electrode forming an electrical contact with the conduction layer; and a gate electrode arranged on top of the structure, between the source electrode and the drain electrode. The structure comprises a bar that is arranged below the gate electrode and passes through the interface of the stack. The bar comprises two semiconductor portions exhibiting opposite types of doping, defining a p-n junction in proximity to the interface.

Abstract: A memory cell including a set of active regions that overlay a set of gate regions to form a pair of cross-coupled inverters. A first active region extends along a first axis. A first gate region extends transversely to the first active region and overlays the first active region to form a first transistor of the pair of cross-coupled inverters. A second gate region extends transversely to the first active region and overlays the first active region to form a second transistor of the pair of cross-coupled inverters. A second active region extends along a second axis and overlays the first gate region to form a third transistor of the pair of cross-coupled inverters. A fourth active region extending along a third axis and overlays a gate region to form a transistor of a read port.

Abstract: An encapsulation hood is fastened onto electrically conductive zones of a support substrate using springs. Each spring has a region in contact with an electrically conductive path contained in the encapsulation hood and another region in contact with a corresponding one of the electrically conductive zones. The fastening of the part of the encapsulation hood onto the support substrate compresses the springs and further utilizes a bead of insulating glue located between the compressed springs.

Abstract: An embodiment level converter circuit is configured to receive, as a current supply, a current proportional to temperature.

Abstract: A clock generator circuit includes an oscillator circuit coupled to a bias circuit. The bias circuit includes a current mirror, third and fourth transistors, and a cascode transistor. The current mirror includes a reference transistor and a set of copy transistors that are programmable. The third transistor has a source connected to a cold spot, a drain and a gate connected to this drain. The fourth transistor has a source connected to the drain of the third transistor, a drain, and a gate connected to that drain. The cascode transistor has a source connected to a drain of at least one of the copy transistors, a drain, and a gate connected to the gate of the fourth transistor. The gates of the fourth transistor and the cascode transistor are thicker than the gates of the reference transistor, each copy transistor, and the third transistor.

Abstract: Described herein is a lock system (e.g., for a vehicle door) including an NFC circuit in communication with a microcontroller that monitors the voltage of a battery (e.g., the vehicle battery). The microcontroller switches the NFC circuit to card emulation (CE) mode with energy harvesting capability when the battery voltage falls below a threshold so that the NFC circuit can harvest energy from a nearby Qi wireless charging field and store that harvested energy in an energy storage device. When the energy storage device is sufficiently charged, it is used power the microcontroller and an electronically actuated mechanical lock (e.g., vehicle door lock), then the microcontroller cooperates with the NFC circuit to switch the NFC circuit to NFC reader mode and attempt to verify a nearby NFC device. If the NFC device is verified, the microcontroller operates the lock, otherwise, it maintains the lock in an inactive state.

Abstract: The present disclosure relates to a cryptographic method comprising: multiplying a point belonging to a mathematical set with a group structure by a scalar by performing: the division of a scalar into a plurality of groups formed of a same number w of digits, w being greater than or equal to 2; and the execution, by a cryptographic circuit and for each group of digits, of a sequence of operations on point, the sequence of operations being identical for each group of digits, at least one of the operations executed for each of the groups of digits being a dummy operation.

Abstract: Cantilever probes are produced for use in a test apparatus of integrated electronic circuits. The probes are configured to contact corresponding terminals of the electronic circuits to be tested during a test operation. The probe bodies are formed of electrically conductive materials. On a lower portion of each probe body that, in use, is directed to the respective terminal to be contacted, an electrically conductive contact region is formed having a first hardness value equal to or greater than 300 HV; each contact region and the respective probe body form the corresponding probe.

Abstract: A method for manufacturing a SiC-based electronic device, comprising the steps of: implanting, on a front side of a solid body made of SiC having a conductivity of an N type, dopant species of a P type thus forming an implanted region, which extends in the solid body starting from the front side and has a top surface coplanar with the front side; and generating a laser beam directed towards the implanted region in order to generate heating of the implanted region to temperatures comprised between 1500° C. and 2600° C. so as to form a carbon-rich electrical-contact region at the implanted region. The carbon-rich electrical-contact region forms an ohmic contact.

Abstract: An in-memory computation circuit includes a memory array with memory cells arranged in a matrix in rows and columns. Groups of memory cells store computational weights for an in-memory compute (IMC) operation that is performed with a first multiply and accumulate (MAC) elaboration to produce a first analog signal and a second MAC elaboration to produce a second analog signal. An analog-to-digital converter circuit operates to: increment a count value in a counter circuit in response to the first analog signal; convert the count value in the counter circuit to a negated count value; and increment the count value in the counter circuit starting from the negated count value in response to the second analog signal.

Abstract: Sensor device with a microcontroller unit and a sensor including a transducer, which is coupleable to a device and generates a signal indicative of a physical quantity, and a processing circuit including: a conversion stage which generates samples of the physical quantity; a data generation stage which generates data vectors as a function of the samples, each data vector being formed by programmable quantity values; and a decision stage. The microcontroller unit programs the decision stage so that it classifies the data vectors by executing a decision tree having a structure and thresholds.

Abstract: The present description relates to a vertical power component formed in and on a semiconductor substrate doped with a first conductivity type and coated, on the upper side thereof, with a semiconductor layer doped with the first conductivity type. The component includes: an active region (100A); and first and second groups of first concentric field limiting rings surrounding the active region. Each first ring includes a first semiconductor region doped with a second conductivity type, opposite to the first conductivity type, extending vertically into the thickness of the semiconductor layer from the upper side thereof; and a second field limiting ring laterally interposed between the first and second groups of first field limiting rings (GR). The second ring includes a second doped semiconductor region of the second conductivity type extending vertically into the thickness of the semiconductor layer from the upper face thereof.

Abstract: The present disclosure relates to an image sensor comprising an array of pixels arranged in first rows and in first columns. The pixels are arranged in groups of N*N pixels, with N an integer equal to or higher than 2. In each group, the pixels of the group are distributed into one or more sub-groups of a plurality of pixels. Each pixel comprises: a photosensitive element, a first node coupled to the photosensitive element, a second node common to all pixels of a same sub-group, and coupled to a first potential, a first transistor coupling the first and second nodes to each other, a second source-follower transistor having a gate connected to the first node, and a third transistor coupling the source of the third transistor to a reading line.

Abstract: A time-of-flight (TOF) sensor includes a timing generator generating a timing reference, a first array of TOF-related components including rows of TOF-related components, with each row receiving the timing reference, and a dummy row of TOF-related components. The TOF sensor also includes a second array of TOF-related components including rows of TOF-related components, with each row receiving the timing reference, and a dummy row of TOF-related components. A first path delivers the timing reference to the rows of the first array, the first path passing from the timing generator, through the dummy row of TOF-related components in the second array, to the first array of TOF-related components. A second path delivers the timing reference to the rows of the second array, the second path passing from the timing generator, through the dummy row of TOF-related components in the first array, to the second array of TOF-related components.