Abstract: A semiconductor device of the type having an integrated circuit with connection terminals connected to metal pads by connecting wires is provided. The integrated circuit includes a substrate-on-insulator type semiconductor substrate having a lower portion on top of which there is an upper insulating layer. A first semiconductor block and a second semiconductor block are produced in the upper insulating layer, and decoupling means are arranged in the upper insulating layer between the first and second semiconductor blocks. The first semiconductor block defines a first capacitor with the lower portion of the substrate, the second semiconductor block defines a second capacitor with the lower portion of the substrate, and the decoupling means includes at least one semiconductor well that defines a decoupling capacitor with the lower portion of the substrate. The capacitance of the decoupling capacitor is higher than the capacitance of each of the first and second capacitors.

Abstract: A filter reduces artifacts, such as grid noise and staircase noise, in block-coded digital images with image block boundaries. The type of filtering is determined after an estimation of the image global metrics and local metrics. For areas of the image near grid noise, the filter performs low pass filtering. For image fine details, such as edges and texture, no filtering is performed so that masking is avoided. The filter operates in intra-field mode and uses a fuzzy logic process, pixel deltas, and dual ramp generators to determine the horizontal and vertical length of a processing window surrounding an image block boundary.

Abstract: A diaphragm-support disc for a polishing machine of the type in which a work piece to be polished is sandwiched between a radial front face of a diaphragm and a polishing surface or cloth. The diaphragm is extended across and wrapped around the peripheral edge of a radial front face of the disc, and a radial rear face of the diaphragm is subjected to pressure from a fluid. The diaphragm-support disc includes a main annular part that projects from the radial front face of the disc and is located in a peripheral region of the radial front face of the disc a predetermined distance from the peripheral edge of the radial front face of the disc. The main annular part can act on the work piece through the diaphragm so as to press the work piece onto the polishing surface or cloth by an axial displacement of the disc with respect to the polishing surface or cloth.

Abstract: In a CMOS process for making dual gate transistors with silicide, high-voltage transistors with drain extensions are produced by first defining on a semiconductor substrate, active areas for low-voltage and high-voltage transistors. A gate oxide layer and a layer of polysilicon is deposited over the substrate, which is masked and etched to produce gates for the transistors. A dielectric layer is deposited to produce spacers to the sides of the transistor gate regions, then a mask partially shields the dielectric layer over the junctions of the high-voltage transistors while the spacers are being formed. Finally, the substrate is doped in the gate and active areas of the high-voltage transistor, and in the gate and active areas of the low-voltage transistor, except those areas that are blocked by the spacers.

Abstract: An electronic level shifter device having very low power consumption includes a first voltage reference from a power supply and a second voltage reference from a ground. The shifter device includes a circuit portion with a differential cell having an output terminal and at least a first and a second input terminal. On the output terminal is a level translated signal with respect to a signal present on one of said input terminals. The device further comprises an additional circuit portion connected to a node of the differential cell and comprising at least a pull-down component inserted between said node and the second voltage reference. The pull-down component can be a MOS transistor having its conduction terminals connected between said node and the second voltage reference and its gate terminal connected to the first voltage reference of power supply by means of a series of transistors.

Abstract: A voltage regulator for memory circuits has a differential stage having a non-inverting input terminal receiving a control voltage independent of the temperature; an inverting input terminal connected to a ground voltage reference; a feed terminal connected to a booster circuit adapted for producing a boosted voltage; and an output terminal connected to an output terminal of the voltage regulator, for producing an output voltage reference starting from the comparison of input voltages. The voltage regulator further comprises a connecting transistor inserted between the feed terminal and the output terminal of the differential stage, the connecting transistor being source follower having a control terminal connected to the output terminal of the differential stage, as well as a source terminal connected to the output terminal of the voltage regulator, in such a way as to self-limit the transition of the voltage on the output terminal.

Abstract: An electronic memory device organized into sections which are in turn divided into blocks formed of cells and their associated decoding and addressing circuits, the cells being connected in a predetermined circuit configuration and each block being included between two opposite contact regions which are interconnected by parallel continuous conduction lines referred to as the bit lines. In the present invention, at least one interruption is provided in each bit line near a contact region by inserting a controlled switch which functions as a block selector. Advantageously, the proposed solution allows each block to be isolated individually by enabling or disabling as appropriate the switches of the cascade connected blocks.

Abstract: An integrated circuit electrically is supplied with a voltage and includes an output MOS transistor having a gate driven by an output of a logic circuit and a circuit for biasing the gate of the output MOS transistor. The circuit for biasing the gate is provided for lowering a gate-source bias voltage of the output MOS transistor in a conductive state in relation to the gate-source bias voltage that would otherwise be provided by the output of the logic circuit. The present invention is particularly applicable to output stages for I2C buses.

Abstract: A circuit extends the output voltage range of an integrator circuit wherein the input signal is used to produce an output signal, and the voltage of the output signal develops monotonically within a predetermined range of possible values. The integrator circuit is driven within an integration time period such that each time the signal at its output reaches a limit of the range of values, the integrator circuit starts a subsequent integration stage of the input signal in which the output signal develops again within the above-mentioned range. This takes place by resetting the integrator circuit or by a reversal of the characteristic slope of the output signal. This is combined with storing the number of occasions on which these interventions have occurred as determined by a counter.

Abstract: A substrate potential limiting device for an integrated circuit that includes a semiconductor substrate is provided. The device includes at least one unidirectional element connected between a substrate contact on the semiconductor substrate and a reference potential. The unidirectional element may be a bipolar transistor. The bipolar transistor includes a base and a collector connected to the at least one substrate contact and an emitter connected to the reference potential.

Abstract: Active areas and body regions are formed in a substrate for forming low voltage MOS transistors, high voltage MOS transistors, and EPROM cells. A thermal oxide layer is formed on the substrate, and a first polycrystalline silicon layer is formed on the thermal oxide layer. The polycrystalline silicon layer is selectively removed to form the floating gate electrodes of the EPROM cells, and the source and drain regions of the EPROM cells are also formed. The active areas for the high voltage MOS transistors are exposed, and a layer of high temperature oxide is formed and nitrided. The active area for the low voltage MOS transistors are exposed, and a layer of thermal oxide is formed on the exposed areas. A second polycrystalline silicon layer is deposited, which is then selectively removed to form the gate electrodes of the low voltage and high voltage MOS transistors, and the control gate electrodes of the EPROM cells.

Abstract: A nonvolatile memory device has a signature code generator generating a present signature code from an algorithm modified dynamically as a function of predefined varying parameters. A variable parameter may be the address of a memory cell being addressed; in this case the output of the code generator is a function of data read from the cell array, the previously calculated signature code and the address of the read data. The data are read in sequence, using an internal clock generated by an internal clock oscillator. In test mode, the memory is scanned sequentially, beginning from any memory location, selected randomly, and the signature code varies in dynamic way; at the end of memory scanning, the signature code is compared to an expected result.

Abstract: A ROM including columns of memory cells connected by columns to respective bit lines; a reference bit line; charge transistors controllable by a common charge line and respectively connecting the bit lines and the reference bit line to a high supply potential. The reference bit line is associated with a column of unprogrammed cells, and the memory includes means for activating the charge line before activation of a word line, the duration between the activation of the charge line and the activation of the word line, and the features of the charge transistors, being chosen so that the level variation of the bit lines is low as compared to the level of the high supply potential.

Abstract: Disclosed are a self-catalytic bath and a method for the deposition of Ni—P alloy on a substrate. The bath comprises nickel sulfate, sodium hypophosphite as a reducing agent, acetic acid as a buffer and traces of lead as a stabilizer. It also includes a citrate used as a complexing agent associated with a gluconate used both as a catalyst and a stabilizer. The disclosed bath makes it possible to tolerate large quantities of hypophosphite and is relatively long-lived. Furthermore, it can be used to prepare large quantities of Ni—P alloy per liter of solution.

Abstract: A process for forming a low resistivity titanium silicide layer on the surface of a silicon semiconductor substrate. In the process, an effective amount of a metallic element such as indium, gallium, tin, or lead is implanted or deposited on the surface of the silicon substrate. A titanium layer is deposited on the surface of the silicon substrate, and a rapid thermal annealing of the titanium-coated silicon substrate is performed to form low resistivity titanium silicide. In preferred processes, the metallic element is indium or gallium, and more preferably the metallic element is indium. A semiconductor device that has a titanium silicide layer on the surface of a silicon substrate is also provided.

Abstract: A method for erasing non volatile memories, in particular flash cells, that includes applying erasing pulses to the cells to be erased and to verify, after each pulse, the value of the threshold voltage of the cells. The erasing pulses are provided to the cells as long as the respective values of the threshold voltage are greater than the new values of threshold voltage corresponding to new data to be rewritten in the cells to be erased.

Abstract: A method for manufacturing electronic devices, such as memory cells and LV transistors, with salicided junctions, that includes: depositing an upper layer of polycrystalline silicon; defining the upper layer, obtaining floating gate regions on first areas, LV gate regions on second areas of a substrate, and undefined regions on the first and third areas of the substrate; forming first cell source regions laterally to the floating gate regions; forming LV source and drain regions laterally to the LV gate regions; forming a silicide layer on the LV source and drain regions, on the LV gate regions, and on the undefined portions; defining HV gate regions on the third areas, and selection gate regions on the first areas; forming source regions laterally to the selection gate regions, and source and drain regions laterally to the HV gate regions.

Abstract: A reference voltage trim circuit includes a voltage follower receiving the reference voltage to be trimmed, with one or more resistive loads providing predefined voltage shifts serially connected between the output of the voltage follower and the output of the trim circuit. The voltage follower includes a current mirror differential amplifier receiving the reference voltage at one input and the output of the voltage follower at the other input, and a transistor with a resistive load connected between the power supply voltages and receiving the output of the current mirror differential amplifier at the transistor's gate. The resistive loads provide varying preselected voltage drop and are each shunted by corresponding fuses, with the entire series of resistive loads shunted by a master fuse. To trim the reference voltage, at least the master fuse is blown, together with the fuse(s) shunting resistive loads which combine to result in the desired trim voltage.

Abstract: A circuit arrangement which, in accordance with its mode of control, operates either as input circuit or as output circuit and includes a series connection with an inverter stage, a filter stage, a cross-current avoiding stage, a switching-on voltage reducing stage, a switch stage, an output driver stage, and a Miller feedback stage, which are configured in the mode of operation as an output circuit, and parallel thereto a Schmitt trigger and an analog switch that can become effective in the mode of operation as input circuit.

Abstract: A process for forming floating gate non-volatile memory cells in a cell matrix with associated control circuitry comprising both N-channel and P-channel MOS transistors is provided. The process includes forming active areas in a substrate for the cell matrix and the associated control circuitry. A first thin oxide layer and a first polysilicon layer are deposited on the active areas to produce floating gate regions of the memory cells, and a second dielectric layer is deposited on the active areas. A second polysilicon layer is then deposited on the active areas. A masking and etching step is performed for exposing the substrate for the associated control circuitry followed by the deposition of a third polysilicon layer. The third polysilicon layer is defined to produce the gate regions of the transistors for the associated control circuitry while the third polysilicon layer is removed from the cell matrix.