Abstract: A redundancy UPROM cell includes at least one memory element of EPROM or Flash type, having a control terminal and a conduction terminal to be biased, an inverter register connected to the memory element by at least one MOS transistor. Such cell also includes a pass transistor which connects said conduction terminal to a data line and a pull-up transistor which connects the data line to a supply voltage reference. The UPROM cell has the great advantage to result in smaller dimensions in comparison with the cells of known type, at equal final functions and performances being assumed.

Abstract: A low noise adaptive bias circuit is provided for a low noise bipolar junction input transistor having an emitter degeneration inductance, of an integrated high frequency functional circuit driven by the collector current of the input transistor. The bias circuit includes a shunt line connecting the base node of the input transistor to a first supply node of opposite sign of that of a second supply node to which is coupled, through the degeneration inductance, to the emitter of the input transistor. The shunt line includes a bias current generator dependent, in an inversely proportional manner, on the current gain of the input transistor, and a resistance dependent, in a directly proportional manner, on the current gain of the input transistor.

Abstract: A method is provided for forming improved quality interlevel aluminum contacts in semiconductor integrated circuits. A contact opening is formed through an insulating layer. A barrier layer is deposited over the surface of the integrated circuit. An aluminum layer is then deposited at relatively low deposition rates at a temperature which allows improved surface migration of the deposited aluminum atoms. Aluminum deposited under these conditions tends to fill contact vias without the formation of voids. The low temperature deposition step can be initiated by depositing aluminum while a wafer containing the integrated circuit device is being heated from cooler temperatures within the deposition chamber.

Abstract: A six transistor static random access memory (SRAM) cell with thin-film pull-up transistors and method of making the same includes providing two bulk silicon pull-down transistors of a first conductivity type, two active gated pull-up thin-film transistors (TFTs) of a second conductivity type, two pass gates, a common word line, and two bit line contacts. The bulk silicon pull-down transistors, two active gated pull-up TFTs, and two pass gates are connected at four shared contacts. In addition, the two bulk silicon pull-down transistors and the two active gated pull-up TFTs are formed with two polysilicon layers, a first of the polysilicon layers (poly1) is salicided and includes poly1 gate electrodes for the two bulk silicon pull-down transistors. A second of the polysilicon layers (poly2) includes desired poly2 stringers disposed along side edges of the poly1 gate electrodes, the desired poly2 stringers forming respective channel regions of the pull-up TFTs.

Abstract: A transconductor includes a differential stage formed by a pair of input transistors, and a resistive line of degeneration connecting the sources of the input transistors. A bias current generator is coupled between the source of each input transistor and ground. The resistive line of degeneration is formed by one or more transistors connected in series, the gates of which are coupled to a voltage reference. The voltage reference is at least equal to the common mode voltage of the differential stage. The one or more transistors forming the resistive line of degeneration are sized to operate in the triode region.

Abstract: In a junction isolated integrated circuit including power DMOS transistors formed in respective well regions or in an isolated epitaxial region on a substrate of opposite type of conductivity, circuits are formed in a distinct isolated region sensitive to oversupply and/or belowground effects. These effects are caused by respective power DMOS transistors coupled to the supply rail or ground. These effects are alternatively controllable by specifically shaped layout arrangements, and may be effectively protected from both effects. This is achieved by interposing between the region of sensitive circuits and the region containing the power DMOS transistors for which the alternatively implementable circuital arrangements are not formed, the region containing the power DMOS transistors coupled to the supply rail or to a ground rail for which the alternatively implementable arrangements are formed.

Abstract: An integrated circuit fuse includes a substantially bar-shaped central region and zones having electrical contacts. The central region includes a thinned zone forming a weak point facilitating fusing of the fuse by increasing the local current density as compared to standard fusing conditions. The thinned zone is preferably obtained by proximity optical effect between the fuse and adjacent dummy elements.

Abstract: A semiconductor power device comprising an insulated gate bipolar transistor, of the type which comprises a semiconductor substrate with a first type of conductivity and an overlying epitaxial layer with a second type of conductivity, opposite from the first, and whose junction to the substrate forms the base/emitter junction of the bipolar transistor, has the junction formed by a layer of semiconductor material with conductivity of the second type but a higher concentration of dopant than that of the epitaxial layer. Furthermore, the device has the epitaxial layer with conductivity of the second type provided with at least two zones at different dopant concentrations, namely a first lower zone being part of the junction and having a higher dopant concentration, and a second upper zone having a lower concentration.

Abstract: An integrated circuit sample package is provided for checking electrical functionality and alignment of a checking device. The checking device includes a contactor and equipment for checking mechanical and electrical features of at least one integrated circuit device. The integrated circuit sample package substantially reproduces the external envelope of the integrated circuit device and is manufactured from an electrical conducting material that is resistant to mechanical wear. In one preferred embodiment, the integrated circuit sample package includes a body that substantially reproduces the external envelope of the body of the integrated circuit device, and offshoots that substantially reproduce the external envelope of the terminals of the integrated circuit device. A method for checking electrical functionality and alignment of a checking device is also provided.

Abstract: A structure of electronic devices integrated in a semiconductor substrate with a first type of conductivity comprising at least a first HV transistor and at least a second LV transistor, each having a corresponding gate region. Said first HV transistor has lightly doped drain and source regions with a second type of conductivity, and said second LV transistor has respective drain and source regions with the second type of conductivity, each including a lightly doped portion adjacent to the respective gate region and a second portion which is more heavily doped and comprises a silicide layer.

Abstract: A neural network including a number of synaptic weighting elements, and a neuron stage; each of the synaptic weighting elements having a respective synaptic input connection supplied with a respective input signal; and the neuron stage having inputs connected to the synaptic weighting elements, and being connected to an output of the neural network supplying a digital output signal. The accumulated weighted inputs are represented as conductances, and a conductance-mode neuron is used to apply nonlinearity and produce an output. The synaptic weighting elements are formed by memory cells programmable to different threshold voltage levels, so that each presents a respective programmable conductance; and the neuron stage provides for measuring conductance on the basis of the current through the memory cells, and for generating a binary output signal on the basis of the total conductance of the synaptic elements.

Abstract: A sense amplifier includes a bistable circuit and a control circuit. The bistable circuit has first and second input/output terminals connected to two input lines via a gating circuit. The bistable circuit has positive and negative supply nodes, one of which is connected to the output of the control circuit. An inverter is connected from the control circuit output to the gating circuit so that the control circuit activates the bistable circuit at all times except when the gating circuit connects the input/output terminals to the input lines.

Abstract: A process forms a structure incorporating at least one circuitry transistor and at least one non-volatile memory cell of the EEPROM type with two self-aligned polysilicon levels having a storage transistor and an associated selection transistor in a substrate of semiconductor material including field oxide regions bounding active area regions. The process comprises the steps of, in the active area regions, forming a gate oxide layer and defining a tunnel oxide region included in the gate oxide layer; depositing and partly defining a first polysilicon layer; forming an interpoly dielectric layer and removing the interpoly dielectric layer at least at the circuitry transistor; depositing a second polysilicon layer; selectively etching away, through a first mask, at least the second polysilicon layer at the cell, and the first and second polysilicon layers at the circuitry transistor; and selectively etching away, through a second mask, the interpoly dielectric layer and the first polysilicon layer at the cell.

Abstract: Embodiments of the invention provide a circuit for generating a trapezoidal signal with controlled wavefronts, particularly for a converter for a satellite receiver, comprising a first oscillator suitable to generate a square-wave signal and a second oscillator which is cascade-connected to the first oscillator, wherein the second oscillator is synchronized with the first oscillator and is suitable to generate a voltage signal which is amplitude-modulated with a trapezoidal modulating signal.

Abstract: A process-independent thermal protection circuit for microelectronic circuits is disclosed, including a thermal ramp generator suitable to generate a first thermal ramp signal and a second thermal ramp signal, a differentiator suitable to determine the difference between the first and second thermal ramp signals in order to generate a difference voltage signal, and a comparator suitable to compare the difference voltage signal with a reference voltage signal in order to assert a thermal protection signal when the difference voltage signal drops below the reference voltage signal.

Abstract: An electric circuit configuration for shaping the slew rate of a pulsed output voltage occurring at an output terminal and for detecting a short circuit at the output terminal, having: a switchover control circuit for controlling the slew rate of the output voltage as a function of a voltage curve occurring across an internal resistor in a first switching state, and for feedback-controlling the slew rate as a function of the output voltage curve in a second switching state, and which is in a substantially dead state in a third switching state; a detector circuit which provides a detection signal when the output voltage differs by at least a predetermined value from the output voltage level occurring before edge onset; and a timer circuit for switching the control circuit from the first to the second switching state a predetermined length of time after edge onset if the detection signal is present at this time, and from the first to the third switching state if the detection signal is not present at this time.

Abstract: A tungsten film stack is formed on a wafer using a deposition chamber by first depositing a nucleation on the wafer in the presence of a carrier gas, such as nitrogen. Following deposition of the nucleation, excess carrier gas is evacuated from the deposition chamber. Then, following evacuation of the excess carrier gas, a tungsten fill is deposited over the nucleation.

Abstract: Presented is a low-drop type of voltage regulator formed with BiCMOS/CMOS technology. The regulator includes an input terminal that receives a stable voltage reference connected to one input of an operational amplifier through a switch controlled by a power-on enable signal. A supply voltage reference powers the operational amplifier. The regulator includes an output transistor connected to an output of the amplifier to generate a regulated voltage value to be fed back to the amplifier input. A second transistor is connected in series between the output transistor and the supply voltage reference. The regulator uses a control circuit portion connected between the control terminal of the second transistor and the supply voltage reference to prevent the breakdown of the output transistor from occurring.

Abstract: In a method of communications between a host system and a memory card with an asynchronous transmission protocol, a message from the card is sent out in response to a control instruction comprising a character or a sequence of several characters in a predetermined format. The protocol is modified so as to have the dispatch of each message or of each character of a message preceded by a detection, by the card, of a response request instruction sent out by the host system.

Abstract: The cell is formed of a selection transistor, a detection transistor and a tunnel condenser. The detection Transistor has its own control gate formed with an n+ diffusion which is closed and isolated from those of the other cells of the same memory.