Abstract: A waveform track-and-hold circuit receives an analog input signal and generates an analog output signal. The waveform track-and-hold circuit includes a differential separating input stage, a differential separating output stage, first and second charge storage means, and switch means. The first and second charge storage means are coupled between the differential separating input stage and the differential separating output stage, and the switch means are controlled by a logic control signal so as to selectively isolate the first and second charge storage means from the analog input signal. Additionally, the differential separating input stage includes a push-pull input stage connected to the switch means and receiving the analog input signal. In a preferred embodiment, the analog input signal is supplied to the emitters of transistors that form the push-pull input stage, the collectors of the transistors are connected to the switch means, and the transistors are part of current mirror circuits.

Abstract: The collector of a vertical bipolar transistor is selectively doped by a first implantation of dopants before the epitaxy of the base, and is selectivly doped by a second implantation of dopants through the epitaxial base. Two implanted zones with different widths are obtained. The base of the vertical bipolar transistor is thinned and the collector resistance is optimized.

Abstract: An ESD protection network protects a CMOS circuit structure integrated in a semiconductor substrate. The circuit structure includes discrete circuit blocks formed in respective substrate portions which are electrically isolated from one another and independently powered from at least one primary voltage supply having a respective primary ground, and from at least one secondary voltage supply having a respective secondary ground. This network includes a first ESD protection element for an input stage of the circuit structure; a second ESD protection element for an output stage of the circuit structure, the first and second protection elements having an input/output pad of the integrated circuit structure in common; a first ESD protection element between the primary supply and the primary ground; and a second ESD protection element between the secondary supply and the secondary ground.

Abstract: A method for forming and bonding a metal bump on a metal pad of an integrated circuit and successively stamping a vertex of the bonded metal bump is performed using the same capillary tool. The dielectric and refractory tip of the capillary tool ends with a flat surface forming a sharp edge adjacent a concave mouth formed therein. A preformed metal ball held in the concave mouth is bonded to the metal pad of the integrated circuit. The method further includes the step of retracting the capillary tool from the bonded metal bump while allowing free movement of the capillary tool relative to the metal wire passing through an axial conduit of the capillary tool. Relative movement of the metal wire is blocked by clamping the metal wire as soon as the capillary tool is pulled off the bonded metal bump. The capillary tool is then laterally shifted for breaking off the metal wire.

Abstract: A protective structure having a plurality of protection regions extending along closed lines arranged inside each other. Each intermediate protective region is tangent to two different adjacent protective regions, at different areas, so as to form a connection in series with the adjacent protective regions. The protective structure can be of resistive material, such as to form a series of resistors, or it can include doped portions alternately of P- and N-type, such as to form a plurality of anti-series arranged diodes. The structure can be made of polycrystalline silicon extending on the substrate surface, or can be integrated (implanted or diffused) inside the substrate.

Abstract: A fabrication process and an integrated MOS device having multi-crystal silicon resisters are described. The process includes depositing a multi-crystal silicon layer on top of a single-crystal silicon body; forming silicon oxide regions on top of the multi-crystal silicon layer in zones where resistors are to be produced; depositing a metal silicide layer on top of and in contact with the multi-crystal silicon layer so as to form a double conductive layer; and shaping the conductive layer to form gate regions, of MOS transistors. During etching of the double conductive layer, the metal silicide layer on top of the silicon oxide regions is removed and the silicon oxide regions form masking regions for the multi-crystal silicon underneath, so as to form resistive regions having a greater resistivity than the gate regions.

Abstract: A semiconductor device is provided which has a plurality of output drivers whose slew rates are differentially controlled. The slew rates of the output drivers are controlled by a control means such that the slew rate of at least one of the output drivers is different than the slew rate of another output driver. Preferably, the slew rates are differentially controlled such that an output driver that drives a signal that reaches an output pin of a semiconductor package later slews at a faster rate than an output driver that drives a signal that reaches an output pin of a semiconductor package earlier. In this way all of the output pins of a semiconductor package can be driven to change states at approximately the same time. The slew rates of the output drivers can be differentially controlled through the utilization of programmable resistors.

Abstract: The memory (MM) is addressed, depending on the format, with address words (MDC) formed at least from the high-order bits of the identifier (ID) of each cue, and possibly padded out with check or selection words (MS) making it possible either to designate consecutive addresses or to select some of the latter from each memory cell (CM) depending on the low-order bits of the identifier. This allows continuous addressing of the memory irrespective of the format used, thereby optimizing the memory size and avoiding a structural or software modification of the addressing system with each change of format.

Abstract: An integrated power operational amplifier can alternatively be operated in a master or a slave mode, such that a master amplifier can be connected in parallel with one or more slave amplifiers. This arrangement allows very low impedance loads to be driven, as well as allowing the heat dissipation to be distributed over a number of operational amplifiers, thereby raising the maximum dissipation limits of integrated power systems. In addition by eliminating the ballast resistors, more power can be delivered by the system, for the same supply voltage, and less power is dissipated.

Abstract: An electronic memory circuit comprises a matrix of EEPROM memory cells. Each memory cell includes a MOS floating gate transistor and a selection transistor. The matrix includes a plurality of rows and columns, with each row being provided with a word line and each column comprising a bit line organized in line groups so as to group the matrix cells in bytes, each of which has an associated control gate line. A pair of cells have a common source region, and each cell symmetrically provided with respect to this common source region has a common control gate region.

Abstract: Circuit for the regulation of the word line voltage in a memory, including a voltage regulator suitable to generate an output regulated voltage to be supplied to one or more word lines of the memory when said one or more word lines are being selected, and charge accumulation means that are selectively connectable with the output of the voltage regulator and suitable to accumulate a compensation charge for a voltage drop that takes place on said regulated voltage upon the selection of said one or more word lines of the memory.

Abstract: A microactuator comprises an outer stator and an inner rotor electrostatically coupled to a stator. The rotor comprises a suspended mass with a substantially circular shape, and a plurality of mobile arms extending radially towards the exterior, starting from the suspended mass. The stator has a plurality of pairs of fixed arms extending radially to the suspended mass, a respective mobile arm being arranged between each pair of fixed arms. The fixed arms are divided into fixed drive arms connected to a drive stage for actuating the microactuator, and into fixed measure arms connected to a measure stage, and define a capacitive uncoupling structure.

Abstract: A circuit for the regulation of the word line voltage in a memory, comprising a voltage regulator suitable to generate an output regulated voltage to be supplied to one or more word lines of the memory when the one or more word lines are being selected. The circuit includes a voltage boosting circuit that is coupled to the output of said voltage regulator and that can be activated upon the selection of one or more memory word lines in order to boost the regulated voltage upon the selection of the one or more memory word lines.

Abstract: A process for forming insulating structures for integrated circuits that includes depositing a silicon oxide layer; shaping the silicon oxide layer to form first delimiting walls of the insulating regions substantially perpendicular to the substrate; and shaping the silicon oxide layer to form second delimiting walls inclined with respect to the substrate. The first walls have an angle of between approximately 70° and 110° with respect to the surface of the substrate; the second walls have an angle of between approximately 30° and 70° with respect to the surface of the substrate 11. The first delimiting walls are formed using a first mask and etching anisotropically first portions of the oxide layer; the second delimiting walls are formed using a second mask and carrying out a damage implantation for damaging second portions of the oxide layer and subsequently wet etching the damaged portions.

Abstract: A circuit and method to drive an H-bridge circuit is disclosed. The H-bridge circuit uses NMOS transistors for both the upper and lower sets of transistors. An inductive head is coupled between the terminals of the transistors. When a logic signal is received, it is boosted with a circuit including a capacitor and is used to drive one of the upper transistors. The upper transistor selected to be driven is responsive to the logic signal. A corresponding lower transistor is also driven, forcing current through the inductive head in a first direction. When the logic signal is received that is the complement of the first logic signal, the other upper and lower transistors turn on, thereby driving current through the inductive head in the other direction. Since all of the transistors in the H-bridge circuit are NMOS transistors, boosted driving circuits are used to quickly change the direction of the flux through the inductive head.

Abstract: A wiring structure has at least three conductors each having a respective first portion running substantially mutually parallel on the first planar path and a second portion, the second portions running substantially mutually parallel on a second planar path to a set of terminals. At least one pair of conductors which are mutually adjacent on the first path are separated on the second path by at least one other of the conductors.

Abstract: Array of electrically programmable non-volatile memory cells, each cell comprising a stacked-gate MOS transistor having a lower gate electrode, an upper gate electrode coupled to a row of the array, a first electrode associated with a column of the array and a second electrode separated from the first electrode by a channel region underlying said lower gate electrode, the first electrode, the second electrode and the channel region being formed in a layer of semiconductor material of a first conductivity type and having a second conductivity type, comprising at least one ROM memory cell which identically to the electrically programmable non-volatile memory cells comprises a stacked-gate MOS transistor and is associated with a respective row and a respective column of the array, the ROM cell including means for allowing or not allowing the electrical separation between said respective column and the second electrode of the ROM cell, if the ROM cell must store a first logic state or, respectively, a second logi

Abstract: Disclosed is a device for performing a header and row correction on rows of sector data that are read sequentially from a DVD medium. The device includes a pair of row buffers, a syndrome generator, and an error correction circuitry. The pair of row buffers sequentially receives and stores a current row of the sector data. When one buffer is receiving a next row of the sector data and is functioning as a receive buffer, the other buffer stores the current row of the sector data and functions as a correction buffer to be used in error correction. The syndrome generator receives the current row of the sector data and is configured to sequentially generate a row syndrome for the current row. The row syndrome is configured to indicates whether an error is present in the current row that is stored in the correction buffer. The error correction circuitry is coupled to the syndrome generator and is configured to receive the row syndrome associated with the current row that is stored in the correction buffer.

Abstract: A method for storing n bytes in multi-level non-volatile memory cells, including writing and reading of said n bytes. Writing includes the following steps: (a) decomposing each one of such n bytes into eight bits, (b) storing each one of such eight bits into a respective one of such multi-level non-volatile memory cells by utilizing a multi-level technology. Reading includes the following steps: (c) reading contemporaneously each one of such eight bits which belong to each one of said n bytes by sense amplifiers each connected to each one of such multi-level non-volatile memory cells, (d) assembling such eight bits previously read to form each one of such initial n bytes.

Abstract: A circuit assembly for an operational amplifier has an input stage with first and second input terminals and an output terminal. An output stage has a first input terminal coupled to the output terminal of the input stage, a second input terminal, and an output terminal. A feedback circuit is coupled between the output terminal of the output stage and the second input terminal of the input stage. An interconnection circuit is coupled to the first and second input terminals and the output terminal of the output stage and to a reference voltage source. The interconnection circuit has first, second, and third modes, such that the second input terminal of the output stage is coupled to the reference voltage source when the interconnection circuit is in the first mode.