Abstract: The present invention relates to a method of formation of a conductive line on integrated circuits including the steps of etching a first insulator layer to create therein openings of predetermined width at the locations where the conductive line is to be formed; depositing and etching a first interconnection layer of a first thickness; and depositing and etching a second interconnection layer of a second thickness; the predetermined width being higher than twice the greatest of the two thicknesses, and lower than twice the sum of the thicknesses.

Abstract: A protection circuit is disclosed for a bipolar power transistor for preventing the operating point thereof from leaving a useful operating area. The protection circuit includes a sense resistor connected between an input supply voltage and a collector of the bipolar power transistor; a first branch circuit, including a first diode connected to the collector of the bipolar power transistor and a first current source connected between a common output node and the first diode; a second branch circuit, including a second diode and a second current source connected between the second diode and the common output node; and a third branch circuit. A short-circuit current level of the bipolar power transistor at relatively low voltage levels of the input supply voltage is based upon current levels for the first current source and the second current source and a resistance value of the sense resistor connected to the bipolar power transistor.

Abstract: A semiconductor memory cell having a word line, a bit line, a precharge line, an access transistor, and first and second cross-coupled inverters. The first inverter includes a first P-channel transistor and a first N-channel transistor, and the second inverter includes a second P-channel transistor and a second N-channel transistor. The access transistor selectively couples the bit line to an output of the first or second inverter, and one terminal of the first N-channel transistor is connected to the precharge line. In a preferred embodiment, a control circuit is provided that, during a writing operation, supplies data to be written to the memory cell to the bit line, supplies a pulse signal to the precharge line, and activates the word line. A method of writing data to a semiconductor memory cell that is coupled to a word line and single bit line is also provided.

Abstract: An intelligent suction device, particularly for vacuum cleaners and the like, includes a fuzzy-logic controller for controlling the motor of a fan or turbine. The suction pressure is detected by at least one pressure sensor which feeds back its measurement, in a closed loop, to the controller.

Abstract: A circuit controls switching of a load between two supply terminals by a device in an emitter-switching configuration formed by a high-voltage bipolar power transistor and a low-voltage switch element. The bipolar power transistor has a collector connected to the load. The switch element has a first terminal connected to the emitter of the bipolar power transistor, a second terminal connected to ground, and a control terminal connected to a control terminal of the circuit. The circuit has a biasing circuit connected to a base terminal of the bipolar power transistor. To ensure that the bipolar power transistor operates in the saturation region throughout the period of conduction, even with a sinusoidal driving voltage, the biasing circuit includes a capacitive device and a charging circuit for charging the capacitive device to bias the base of the bipolar power transistor.

Abstract: A low-cost semiconductor user input device for controlling the position of a pointer on a display includes a small array of composite sensors. Each composite sensor of the array is adapted to detect movement of a fingerprint feature. The user input device moves the pointer based upon the net movement detected by the composite sensors of the array.

Abstract: Presented is a circuit device for driving an a.c. electric load, incorporating a rectifying bridge that has a first input connected to one terminal of the electric load and a second input connected to an outlet of an a.c. main supply. The rectifying bridge has output terminals connected to a power switch which is controlled by an electric signal. The circuit device has a circuit loop-back link connected in parallel to the electric load, and a second circuit loop-back link connected in parallel to the electric load. The first and second links are alternately activated by the positive and negative half-waves of the main supply when the switch is in its “off” state.

Abstract: A process for polishing, on a polishing machine and under defined polishing conditions, the external surface of at least one wafer of integrated circuits comprising a projecting feature covered over the entire surface of the wafer with an external layer of a material, consisting in calculating a main equivalent thickness equal to the main surface density of the projecting feature multiplied by the thickness of the latter; in polishing, under the defined polishing conditions, a reference wafer comprising an external layer of the material, having a uniform thickness and covering the surface of this reference wafer, so as to determine the rate of removal by the polishing machine corresponding to the ratio of the thickness removed to the polishing time elapsed; in calculating a polishing time equal to the ratio of the aforementioned equivalent thickness to the aforementioned rate of removal; in calculating a total equivalent thickness equal to the sum of the main equivalent thickness and of a complementary thickn

Abstract: The anti-pop circuit includes a unity gain buffer with an input coupled to the source of the reference voltage and an output coupled to the input of the amplifier to accelerate the charging of the input coupling capacitor of the amplifier at every turn-on. The capacitor-charging buffer is automatically disabled before the turning-on of the amplifier. The charging buffer may be enabled at start up by generating an impulse of a pre-established duration at the turn-on instant by a monostable circuit or by disabling it upon verifying the decaying to zero of the charging of current of the input coupling capacitor. The circuit eliminates the popping noise at the turn-on without an excessive delay of the turning-on of the amplifier.

Abstract: The driving capability of a selection transistor is increased by an N-type implant at the source and drain regions of the selection transistor itself. This implant is conveniently made at the end of the self-aligned etching, using the same self-aligned etching mask defining the control gate regions and the floating gate regions of memory elements, keeping the circuitry area covered by a circuitry mask.

Abstract: A semiconductor non-volatile memory device that includes memory cells and selection transistors. The memory cells each include a floating gate transistor having an active area, source and drain regions, a floating gate, and a control gate, and each of the floating gate transistors is serially coupled to one of the selection transistors. A contact to the control gate is located above the active area. In a preferred embodiment, the contact is substantially aligned with a central portion of the active area. A method for manufacturing a non-volatile memory device on a semiconductor substrate is also provided. According to the method, a poly1 layer is deposited, an interpoly dielectric layer is deposited above the poly1 layer, and a poly2 layer is deposited above the interpoly dielectric layer. A mask is provided to define the control gate, and a Self-Aligned poly2/interpoly/poly1 stack etching is used to define a gate stack structure that includes the control gate and the floating gate.

Abstract: The process for fabricating a network of nanometric lines made of single-crystal silicon on an isolating substrate includes the production of a substrate comprising a silicon body having a lateral isolation defining a central part in the body. A recess is formed in the central part having a bottom wall made of dielectric material, a first pair of opposed parallel sidewalls made of dielectric material, and a second pair of opposed parallel sidewalls. At least one of the opposed parallel sidewalls of the second pair being formed from single-crystal silicon. The method further includes the epitaxial growth in the recess, from the sidewall made of single-crystal silicon of the recess, of an alternating network of parallel lines made of single-crystal SiGe alloy and of single-crystal silicon. Also, the lines made of single-crystal SiGe alloy are etched to form in the recess a network of parallel lines made of single-crystal silicon insulated from each other.

Abstract: A voltage regulator with a current limiter includes a voltage regulating circuit including an amplifier circuit and a feedback circuit. The amplifier circuit includes a ballast or pass resistor and the feedback circuit supplies a first feedback voltage to the amplifier circuit, which is compared to a reference voltage. The voltage regulator further includes a current limiter circuit including a current limiter transistor in series with the ballast transistor and an output of the voltage regulator and a feedback circuit supplying a second feedback voltage to a controller for controlling the current limiter transistor. The controller causes the current limiter transistor to operate between saturation and blocking conditions depending on whether the second feedback voltage, which is representative of the output of the voltage regulator, is above or below a predetermined threshold voltage.

Abstract: A system for preventing crosstalk noise in a head of a drive for a reading data from and writing data to a magnetic media. The present invention includes circuitry that applies an intermediate current to a write element after a write operation is complete. The intermediate current causes the magnetic domains of the write element to go from a high energy state to an intermediate energy state before going to a low energy state. This reduces the magnetic pulses emitted from the write element.

Abstract: An integrated control and regulation circuit for a power stage of a regulated power supply, includes a current generator which, when the power supply is switched on, charges a decoupling capacitor to decouple a power stage of the power supply, through a first switch. The output from a logic circuit controls this first switch, and opens it when the regulated output voltage from the power stage reaches its nominal value. Preferably, a second switch controlled by the same output from the logic circuit deactivates a regulation loop of the power stage during the start up phase and in the case of a short circuit.

Abstract: According to the present invention, by setting the logic state of one or more delay signals to appropriate values, the resistive value of a plurality of power supply delay elements throughout an integrated circuit having distributed circuit blocks may be modified to produce desired delay times or pulse width adjustments throughout the integrated circuit. Setting delay signals to desired logic states may be accomplished by a variety of means including forcing test pads to a logic level, blowing fuses, or entering into a test mode.

Abstract: A peripheral device connecting system with priority arbitration includes a connection matrix connected to a plurality of peripheral devices capable of transmitting a signal to be arbitrated, e.g., an interrupt enable signal. The connection matrix includes first and second connection matrices connected to each other through a plurality of logic gates having a progressive number of inputs for transmitting in parallel a plurality of signals to be arbitrated. A connection matrix for a microcontroller-emulating chip includes a peripheral device connecting system with priority arbitration.

Abstract: A method and circuit is disclosed for controlling the write head of a magnetic disk storage device. The circuit includes a pull-up device coupled to a terminal of the write head, for selectively providing a current to the write head through the terminal. The circuit further includes parallel-connected first and second current sink circuits, each of which is coupled to the write head terminal and selectively activated to draw current from the write head via the write head terminal. The circuit further includes a control circuit for individually activating the pull-up device and the first and second current sink circuits. In particular, when reversing the direction of current flow through the write head from a first direction in which current is provided to the write head via the write head terminal to a second direction in which current is drawn from the write head from the write head terminal, both the first and second current sink circuits are activated by the control circuit.

Abstract: A circuit for measuring a propagation time of an edge of a signal between an input and an output of a logic cell. The circuit includes a plurality of logic cells of a first type that are electrically coupled in a series, and a plurality of multiplexers, each having a selection input, first and second data inputs, and an output. Each of the plurality of logic cells has a first input and an output, the output of each logic cell in the series being respectively electrically coupled to the first input of a next logic cell in the series. The output of a last logic cell in the series is electrically coupled to the first input of a first logic cell in the series to form a ring. The selection input of each multiplexer of the plurality of multiplexers is electrically coupled to the output of one logic cell in the series, with the output of each multiplexer being electrically coupled to the first input of the next logic cell in the series.

Abstract: A design for an overvoltage protection circuit can be used to fabricate several different circuits incorporating different protection techniques. The design is suitable for use in a single device, which can be easily and inexpensively packaged and protected from the environment. Three terminal protection circuits can have three terminals on an upper surface of a substrate, or one terminal on a lower surface of the substrate, using a single modular design. Additional circuitry can be included to sense for high current conditions which are caused by overvoltages too low to trigger the normal overvoltage protection circuits.