Abstract: An SRAM cell includes a pair of N channel transistors acting as inverting circuits, a pair of N channel transistors which perform the control function for the cell, and a pair of N channel thin film transistors in depletion mode with gate and source shorted to provide load devices for the N channel inverter transistors of the SRAM cell.

Abstract: The present invention relates to an integrated circuit including at least one logic circuit, able to operate at a first operating frequency, and a clock distribution circuit, the clock distribution circuit receiving a first clock signal and providing to the logic circuit a second clock signal, generated from the first clock signal, the frequency of the second clock signal being substantially equal to the first operating frequency. The clock distribution circuit includes a frequency multiplying circuit for generating the second clock signal, so that the frequency of the first clock signal may be lower than the first operating frequency to reduce or minimize the power consumed by the clock distribution circuit.

Abstract: The charge injection circuit of this invention comprises at least one pair of floating gate MOS transistors having source and drain terminals which are coupled together and to an injection node, and at least one corresponding pair of generators of substantially step-like voltage signals having an initial value and a final value, and having outputs respectively coupled to the control terminals of said transistors. The signal generators are such that the initial value of a first of the signals is substantially the equal of the final value of a second of the signals, and that the final value of the first signal is substantially the equal of the initial value of the second signal.

Abstract: A process of manufacturing cross-point matrix memory devices which have floating gate memory cells having the source channel self-aligned to the bit line and the field oxide is disclosed. The process includes the steps of growing a thin layer of tunnel oxide on the matrix region; depositing a stack structure comprising a first conductive layer, an intermediate dielectric layer, and a second conductive layer; photolithographing with a Polyl mask to define a plurality of parallel floating gate regions in the stack structure; self-aligned etching of the stack structure, above the active areas, to define continuous bit lines; and implanting, to confer predetermined conductivity on the active areas . Advantageously, the self-aligned cascade etching step for removing parallel strips from multiple layers, down to the active areas of the substrate, is discontinued before the field oxide is removed, and the implantation step is carried out in the presence of field oxide over the source active areas.

Abstract: A manufacturing method having the steps of: depositing an upper layer of polycrystalline silicon; defining the upper layer, obtaining LV gate regions of low voltage transistors and undefined portions; forming LV source and drain regions laterally to the LV gate regions; forming a silicide layer on the LV source and drain regions, on the LV gate regions, and on the undefined portions; defining salicided HV gate regions of high voltage transistors; and forming HV source and drain regions not directly overlaid by silicide portions.

Abstract: A process for manufacturing a MOS transistor and especially a MOS transistor used for non-volatile memory cells is presented. At the start of the manufacturing, a semiconductor substrate having a first type of conductivity is covered by a gate oxide layer. A gate electrode is formed over the gate oxide layer, which is a stacked gate when the MOS transistor is used in a non-volatile memory. Covering the gate electrode is a covering oxide that is formed over the gate oxide layer, the gate electrode, and around the gate electrode. Next, a dopant of a second type of conductivity is implanted to provide implant regions adjacent to the gate electrode. Subjecting the semiconductor to thermal treatments allows the implanted regions to diffuse into the semiconductor substrate under the gate electrode and form a gradual junction drain and source region of the MOS transistor.

Abstract: A one-way switching circuit of the type including a gate tun-off thyristor biased to be normally on, further includes, between the gate and a supply line, a capacitor and a controllable switch connected in parallel.

Abstract: A interconnection structure of the damascene type is produced on a surface of a microelectronic device that includes at least one dielectric material layer for housing at least one interconnection and at least one interface layer on the dielectric material layer. The interface layer may include at least one SiCH layer and at least one SiOCH layer.

Abstract: A master-slave D type flip-flop circuit includes a power consumption circuit including a reference stage in parallel with a master and a slave stage of the flip-flop circuit. This structure advantageously provides a switching of the flip-flop circuit on each of the leading and trailing edges of the clock signal for the sequencing of the flip-flop circuit.

Abstract: An address latch enable signal control circuit for electronic memories, including: a circuit for sensing an external address latch enable signal; a switching circuit connected in output to the sensing circuit; an address storage circuit, connected in output to the switching circuit and to the address sensing circuit; the switching circuit being suitable to determine the switching between a first circuit path and a second circuit path for connection between the address sensing circuit and the address storage circuit; the first circuit path connecting the sensing circuit directly to the storage circuit across the switching circuit; the second circuit path connecting the sensing circuit to the storage circuit with a delay circuit interposed, the delay circuit being suitable to produce a time delay in the connection between the address sensing circuit and the address storage circuit, the sensing circuit being suitable to generate an internal address latch enable signal meant to be stored in is the storage circuit

Abstract: A suppression method is applied to an integrated circuit formed on a substrate of p-type material having at least one region of n-type material with junction isolation, a first electrical contact on the frontal surface of the substrate, a second electrical contact on the n-type region and a third electrical contact on the back of the substrate connected to a reference (ground) terminal of the integrated circuit. To avoid current in the substrate due to the conduction of parasitic bipolar transistors in certain operating conditions of the integrated circuit, the method provides for monitoring the potential of the second contact to detect if this potential departs from the (ground) potential of the reference terminal by an amount greater than a predetermined threshold value. If this occurs the first contact is taken to the potential of the second contact, otherwise they are held at the (ground) potential of the reference terminal. A device and an integrated circuit which utilize the method are also described.

Abstract: A data recovery system wherein the data is represented by a sequence of preamble pulses having a predetermined sequence followed by data pulses. An analog to digital converter converts samples of the preamble pulses and the data pulses into corresponding digital words in response to clock pulses fed to a clock input of the converter. A pair of feedback loops is coupled to an output of the analog to digital converter to produce the clock pulses for the converter; a first one during a data recovery mode and a second one during a preceding preamble acquisition mode.

Abstract: A method of removal of polymers of the type including bromine, chlorine, silicon, and carbon, present on a semiconductor wafer partly covered with resist, including of rotating the wafer in its plane around its axis, in an enclosure under a controlled atmosphere, at ambient temperature, including the steps of rotating the wafer at a speed included between 500 and 2000 CPM in an enclosure filled with nitrogen; sprinkling the wafer with water, substantially at the center of the wafer; introducing hydrofluoric acid during a determined cleaning time, while maintaining the sprinkling; and rinsing the wafer by continuing the sprinkling to remove any trace of hydrofluoric acid from the wafer, at the end of the cleaning time.

Abstract: A start-up routine is provided for a multiphase brushless DC motor having one or more rotor position sensors insufficient to provide for an angular resolution as high as the angular resolution of the synchronized driving system of the motor. The start-up routine includes setting at least an angular check zone having a certain arc length angularly correlated to the one or more rotor position sensors, assuming a certain initial rest position of the rotor, and exciting for fixed time intervals the phase windings in a sequence for rotating the rotor toward an angular position next to the initial position. This routing is performed in the desired direction while masking the signals from the one or more rotor position sensors for a preestablished masking time.

Abstract: Presented is a voltage regulating circuit for a capacitive load, which is connected between first and second terminals of a supply voltage generator. The regulating circuit has an input terminal and an output terminal, and includes an operational amplifier having an inverting input terminal connected to the input terminal of the regulating circuit and a non-inverting input terminal connected to an intermediate node of a voltage divider. The voltage divider is connected between an output node, which is connected to the output terminal of the regulating circuit, and the second terminal of the supply voltage generator. The operational amplifier has an output terminal connected, for driving a first field-effect transistor, between the output node and the first terminal of the supply voltage generator. The output terminal of the operational amplifier is also connected to the output node through a compensation network.

Abstract: A method is provided for generating a pulse signal with modulable-width pulses. A set-point signal is generated and compared with a control signal so as to produce the pulse signal. When the control signal is a two-state logical signal, a first reference voltage is taken as the set-point signal. When the control signal is a continuous analog voltage, the set-point signal is varied between the first reference voltage and a predetermined second reference voltage, which is higher than the first reference voltage. Also provided is a device for generating a pulse signal with modulable-width pulses. The device includes a set-point signal generator, a control signal generator, and a comparator that outputs the pulse signal. The set-point signal generator includes a first voltage source for generating a first reference voltage, and a second voltage source for generating a second reference voltage, which is higher than the first reference voltage.

Abstract: In a computer system, a processing unit generates a read request and sends it to a cache. If data for the read request is not in the cache, the cache forwards the request to a bus interface unit. If the forwarded request does not fall within the address range of any bus read transaction stored in the bus interface unit, the bus interface unit stores a new bus read transaction corresponding to the forwarded request and sends an identifier for the new transaction to the processing unit. In one preferred embodiment, if the forwarded request falls within the address range of one of the bus read transactions stored in the bus interface unit, the bus interface unit discards the forwarded request and sends an identifier for the one transaction to the processing unit. Additionally, a method of processing read requests is provided. A read request is stored in a buffer and sent to a cache.

Abstract: An integrated semiconductor device comprises, reciprocally superimposed, a thermally insulating region; a thermal conduction region of a high thermal conductivity material; a passivation oxide layer; and a gas sensitive element. The thermal conduction region defines a preferential path towards the gas sensitive element for the heat generated by the heater element, thereby the heat dispersed towards the substrate is negligible during the operation of the device.

Abstract: Circuit for discharging to ground, supplied by a supply voltage, comprising a reference voltage, a negative potential node, first circuitry adapted to couple the negative potential node to the reference voltage in response to a control signal. Second circuitry is provided adapted to determine in the first circuitry the passage of a controlled current for the discharge of the negative potential node.

Abstract: A secured electrically modifiable non-volatile memory includes a circuit to determine if memory cells therein have been exposed to ultraviolet radiation. The memory includes at least one additional memory cell, called a reference cell, and an associated read circuit for detecting any erasure of the reference cell by ultraviolet radiation. At each access to the memory, the reference cell is read by the associated read circuit. If the state of the reference cell is different from its initial electrical state, then operation of the memory is stopped.