Abstract: The present invention relates to a device of protection of a monolithic component including a MOS-type vertical diffused power transistor formed of a great number of identical cells, and a measurement transistor formed of a smaller number of cells identical to those of the power transistor, the drains and the gates of all cells being common, an inductive load being connected to the source of the power transistor, a short-circuiting circuit connected between the source of the power transistor and the source of the measurement transistor, and a control circuit that turns on the short-circuiting circuit when the power transistor turns off.

Abstract: Circuitry is described for transferring information from a first timing environment to a second timing environment. The circuitry comprises a dual port RAM having a first port which is responsive to a first timing signal and a second port which is responsive to a second timing signal, a first control circuit which is responsive to the first timing signal, for controlling storage of data in the dual port RAM through the first port and for generating a control signal indicating that data is stored in the dual port RAM. The circuitry also comprises a synchronizer for synchronizing the control signal to the second timing signal, and a second control circuit, which is responsive to the second timing signal and the synchronized control signal and is for controlling retrieval of stored data through the second port of the dual port RAM.

Abstract: A method of integrated circuit assembly before encapsulation including at least one step of soldering, under mechanical pressure, a first element on a second element, including temporarily maintaining a predetermined spacing, at least partially without solder paste, between the surfaces to be assembled of the first and second elements.

Abstract: A method drives a three-phase motor having first, second, and third coils. The method electrically connects the first coil to a first voltage reference and the second coil to a second voltage reference while leaving the other coil floating during a first driving phase. During a second driving phase, the first coil is electrically connected to the first voltage reference and the third coil is electrically connected to the second voltage reference while the second coil is left floating. During a transition phase that immediately follows the fast driving phase and immediately precedes the second driving phase, the second coil is electrically connected alternately to the first and second voltage references. By alternately connecting the second coil to the first second voltage references and during the transition phase, the method causes the current through the second coil to reduce to zero at a slower rate than prior methods.

Abstract: With a switch including at least one insulated-gate field-effect transistor, an analog input signal is delivered on the source of the transistor and the transistor is controlled on its gate synchronized with a clock signal to successively turn it on and off. On the conclusion of each half-period of the clock signal during which the transistor is off, a precharging capacitor is precharged at the start of the next half-period and for a predetermined precharge duration, with a predetermined precharge voltage. Then, for the remaining duration of the half-period, the precharged capacitor is connected between the source and the gate of the transistor to turn it on under the action of a gate-source voltage which is almost independent of the level of the input signal. At the end of the half-period, the gate of the transistor and the precharging capacitor are grounded.

Abstract: In an electronic component including a two-way bus through which data elements travel between peripherals and a central processing unit at the rate of a clock signal, the central processing unit and at least one of the peripherals each includes a data encryption/decryption cell. Each data encryption/decryption cell uses the same secret key. The secret key is produced locally at each clock cycle in each cell from a random signal synchronous with the clock signal, and is applied to each of the cells by a one-way transmission line.

Abstract: A circuit for detecting the disappearing of a periodic input signal, the circuit including a frequency divider receiving the input signal, the frequency divider having two complementary outputs combined with a same reference signal of same frequency as the input signal by means of two respective similar logic gates, the output of a first one of the logic gates being connected to increment a first counter and to reset a second counter similar to the first one, and the output of the second logic gate being connected to increment the second counter and to reset the first counter, and a logic circuit generating a disappearing detection signal when any one of the two counters reaches a predetermined value.

Abstract: A driver circuit for controlling a piezoelectric actuator in a charge mode includes an amplifier having a first input terminal for receiving a control voltage, a second input terminal, and a main final stage with a main output terminal connected to the piezoelectric actuator. The amplifier also includes an additional final stage with an additional output terminal connected to the second input terminal. The main final stage and the additional final stage are connected in parallel with one another so that a current which passes through the main output terminal is proportional in accordance with a predefined factor to a current which passes through the additional output terminal. The driver circuit includes a device having a constant capacitance connected to the second input terminal so that an electrical charge transferred to the piezoelectric actuator is correlated with the control voltage in accordance with the predefined factor and the capacitance.

Abstract: The present invention relates to an integrated circuit test pad implemented in a surface metallization layer covered with an insulating coating. The pad is surrounded with a first metal ring made in the surface metallization layer and with a second metal ring made in a lower metallization surface, the first and second rings being electrically interconnected by at least one via and set to a fixed potential.

Abstract: A converter of a high A.C. voltage into a low D.C. voltage, including a one-way switch between a first terminal of application of the A.C. voltage and a first positive output terminal, and circuitry for controlling the output voltage to a desired value, the one-way switch being controlled in linear mode.

Abstract: A method and circuit are disclosed for maintaining stored data within a ferroelectric memory device. The circuit includes a first circuit for selectively logically inverting the data in the ferroelectric memory device. A second circuit enables the first circuit at the one or more predetermined times. A third circuit logically inverts data to be written to and data read from the ferroelectric memory device following every other predetermined time. In this way, the circuit is capable of inverting the data values stored in the ferroelectric memory device, thereby reducing the susceptibility of imprint.

Abstract: A processor that includes an instruction extraction stage, an instruction register, an instruction decoder, a first multiplexer that supplies the instruction register, and an autonomous counter with a presetting register. The first multiplexer receives the output of the extraction stage and the output of the instruction register, and the instruction decoder receives the output of the instruction register. Additionally, a first circuit produces a repetition signal if a received instruction is a repetition instruction, and a second circuit outputs a value from the received instruction to the presetting register when the received instruction is a repetition instruction. A third circuit produces an instruction execution signal that is supplied to the counter, and the first multiplexer is controlled so as to supply the instruction register based on a control output of the counter. The present invention also provides a method of handling instructions to be repeated by a processor.

Abstract: Parallel processing in the form of two PR4 Viterbi Detectors connected in parallel operates to increase the maximum channel speed of a given data channel of a magnetic media. According to a target equation defined as Read(D)=(1−D2)2Written(D), in which D is the delay of a data of the channel, a first Viterbi Detector processes even data samples of the channel that have been equalized according to the target equation and a second Viterbi Detector connected in parallel processes odd data samples of the channel that have likewise been equalized according to the target equation. The use of two parallel-connected Viterbi Detectors in this fashion allows data to be processed at half-rate rather than full-rate, thereby increasing the overall channel speed.

Abstract: A programmable-gain multistage amplifier with broad bandwidth and reduced phase variations having a differential input stage biased by a first current source and to which a differential voltage signal is fed, the stage being connected to a pair of diodes in which the cathode terminals are connected to respective bipolar transistors, which are biased by a second current source and in which the collector terminals are connected to load resistors, the differential output of the amplifier being provided at the collector terminals of the bipolar transistors.

Abstract: An integrated circuit structure and method is capable of automatically tuning the duty cycle of a generated clock signal to any desired value. Tuning of the duty cycle depends upon the precise layout specifications of multiple delay elements of one or more multiplexing circuits of the integrated circuit device. Connecting one or more multiplexing circuits in a serial fashion allows a base frequency to be multiplied in order to produce a generated clock frequency of a desired frequency. Control of select lines to the multiplexing circuits allows the delay path through the one or more multiplexing circuits to be adjusted, thereby automatically adjusting the duty cycle of the generated clock signal.

Abstract: A method of processing a bitstream of coded data of video sequences of progressive or interlaced pictures includes estimating motion vectors of groups of pixels. These groups of pixels belong to a top half-frame of the current picture in relation to pixels belonging to a bottom half-frame of a preceding picture. Motion vectors are also estimated for group of pixels of a bottom half-frame of the current picture in relation to pixels belonging to the top half-frame of the current picture. The processing calculates for each macroblock of a top half-frame and a bottom half-frame a respective top motion coefficient and a bottom motion coefficient depending on the estimation of the motion vectors of the top half-frame and the bottom half-frame. The current picture is recognized as an interlaced picture by a substantial equality of the distributions of values of the motion coefficients, or as a progressive picture by a substantial inequality of the distributions of values of the motion coefficients.

Abstract: A system architecture for a high speed serial bus compatible with the 1394 standard is disclosed. A transaction interface coordinates data packets received from or sent to a 1394 bus. A kernel/scheduler/dispatcher is used to allocate memory resources, and start a variety of tasks and services. The tasks and services vary depending on protocols used in a transport layer and application layer used in conjunction with the 1394 layers. Each task operates according to a state machine progression. The transaction interface accepts data information from the tasks and forms data packets for delivery to the 1394 bus. The data packets are initially sent via an associated hardware register, but if busy, the transaction interface polls for other available registers. In addition, all queued transactions are loaded into registers in the most expedient manner.

Abstract: An equalization control circuit having an equalization signal generating stage having an enabling input receiving an address transition signal, a disabling input receiving a disabling signal, and an output generating an equalization control signal. An auxiliary line is supplied at one initial terminal (35a) with a biasing voltage correlated to the reading voltage supplied to the addressed array cell. An equalization filter is connected to the end terminal of the auxiliary line and generates the disabling signal when the voltage at the end terminal of the auxiliary line exceeds a preset threshold value.

Abstract: A method and a related circuit structure are described for improving the effectiveness of ESD protection in circuit structures realized in a semiconductor substrate overlaid with an epitaxial layer and including at least one ESD protection lateral bipolar transistor realized in the surface of the epitaxial layer. The method consists of forming under the transistor an isolating well that isolates the transistor from the substrate. Advantageously, the transistor can be fully isolated from the substrate by first and second N wells which extend from the surface of the epitaxial layer down to and in contact with the buried well.

Abstract: A selector switch monolithically integrated to a CMOS technology circuit for electrically programmable memory cell devices having at least first and second input terminals for coupling to first and second voltage generators (HV and LV), respectively, and an output terminal. First and second field-effect selection transistors are respectively connected, via first and second terminals, between the first input terminal and the output terminal and between the second input terminal and the output terminal. These transistors are driven through control terminals at non-overlapping phases and have body terminals connected at a body circuit node which is coupled to the first and second voltage generators through a bias circuit block effective to bias the node to the higher of the instant voltages generated by the first and second generators.