Abstract: Interlevel contacts in semiconductor integrated circuits are fabricated by formation of a contact opening through an insulating layer. A layer of refractory metal, or refractory metal alloy, is deposited over the surface of the integrated circuit chip. An aluminum layer is then deposited at a significantly elevated temperature, so that an aluminum/refractory metal alloy is formed at the interface between the aluminum layer and the refractory metal layer. Formation of such an alloy causes an expansion of the metal within the contact opening, thereby filling the contact opening and providing a smooth upper contour to the deposited aluminum layer.

Abstract: A redundant circuit and method for a semiconductor memory device is disclosed. The redundant circuit includes a programmable circuit for selectively generating at least one first address corresponding to a defective memory row or column line, and shifter circuitry for remapping second addresses which are greater than the first address to row/column lines. For each second address which is greater than the first address, the shifter circuitry remaps the second address to a row/column line which was initially mapped to an immediately higher address relative to the second address. The programmable circuit is capable of generating a plurality of first addresses corresponding to a plurality of defective memory row or column lines.

Abstract: A method of controlling the operations of an on-chip memory unit includes the steps of receiving an indication of at least the ready or busy state of the memory unit and instructing the memory unit to perform the next operation once the indication is of the ready state. The step of receiving can include the repeated steps of capturing the indication and the data and address information of the previous byte provided to the memory unit and shifting the data and address information of a next byte and at least one extra bit through a shift register such that the indication is also shifted out of the shift register to a data out pin of a JTAG port. The steps of capturing and shifting, which provide double buffering, are repeated until the indication is of the ready state. Alternatively, the step of receiving occurs from a non-JTAG port of the chip to a pin on a receiving port. The present invention includes the chip which can operate according to the steps of the method.

Abstract: The process proposed allows provision of a matrix topography for electronic memory devices using self-alignment etchings capable of removing those spurious electrical contacts between adjacent memory cells. The self-aligned etching process proposed for providing a plurality of mutually parallel word lines in a first conducting layer deposited over a planarized architecture obtained starting from a semiconductor substrate. Provided on the semiconductor substrate is a plurality of active elements extending along separate parallel lines, e.g., memory cell bit lines, and comprising gate regions formed by a first conducting layer, a dielectric interpoly layer and a second conducting layer with said regions being insulated from each other by dielectric insulation films to form said architecture with said word lines being defined photolithographically by protective strips.

Abstract: An integrated antenna structure wherein a metallic RF antenna provides part of the package structure for an RF transmit/receive chip. The requirement for a separate package to house the driver chip as well as for the wire or cable between the driver chip and the antenna are eliminated. The antenna itself provides a convenient heat sink. This arrangement is particularly attractive at UHF frequencies.

Abstract: An EEPROM cell with improved current performance, the EEPROM cell having: a selection transistor with a drain region, a source region and a control gate, a memory cell having a drain region, a source region, a control gate and a floating gate, the drain region of the memory cell and said source region of the selection transistor are connected together, and the source and drain regions of the memory cell and the source and drain regions of the selection transistor share an active area with a pair of sides that linearly converge from one end to the other end

Abstract: A method for characterizing a structure including single-crystal silicon-germanium areas on a single-crystal silicon substrate, including the steps of measuring the X-ray diffraction spectrum of the structure, simulating the diffraction spectrum of a single-crystal silicon substrate, simulating the diffraction spectrum of a single-crystal silicon substrate entirely coated with a single-crystal SiGe layer, adding the simulated spectrums while assigning them weights a and 1-a to obtain a sum spectrum, comparing the sum spectrum with the measured spectrum and adjusting the simulation parameters and weight a to reduce the distance between the sum spectrum and the measured spectrum, and after optimizing, adopting the simulation parameters as the measurement parameters.

Abstract: A circuit and method are disclosed for controlling bootstrap circuitry that boosts a voltage level appearing on word lines of a dynamic random access memory device. During execution of a memory access operation, the circuit is adapted to enable the bootstrap circuitry a period of time following the memory device's sense amplifiers initially powering up. The circuit senses when the voltage appearing on a select bit line crosses a predetermined voltage level, and enables the bootstrap circuitry thereafter. In this way, a period of time elapses between the sense amplifiers turning on and the activation of the bootstrap circuitry, thereby reducing noise introduced from the sense amplifiers turning on from impacting the operation of the bootstrap circuitry.

Abstract: A negative load pump circuit includes switching MOS transistors and capacitors. Each switching transistor is formed in a well on an integrated circuit, and each transistor has its well contact or body connected to its gate and to its source to receive a phase signal. The device advantageously includes a circuit for the regulation of the negative load pump circuit. This maintains the negative load pump circuit in stopped conditions corresponding to minimum power consumption, and enables a speedy supply of a negative low level expected at the output of the negative load pump circuit for an intended application. This is based upon activation by an external command.

Abstract: The invention relates to a method and a device for recognizing and warning of the level of fullness of a waste container in a suction system driven by a motor and provided with an internal chamber kept under suction pressure and comprising the waste container. The method foresees a measurement of the difference of pressure between the internal chamber and the environment outside the vacuum cleaner and an elaboration of such measurement according to a set of rules in fuzzy logic for producing an electric warning signal corresponding to the filling level of the waste container.

Abstract: A cyclic redundancy check value is computed by iterating a loop in which the contents of an operand having a first CRC value and a data value are shifted 1 bit to the end at which the CRC value is located. A generator value is exclusive-RED into corresponding respective bits of the operand only if the bit shifted out of the operand by the shift was set. This is repeated until a data byte has been displaced entirely and a modified cyclic redundancy check value occupies the most significant bytes, but now incorporates the original data byte in modified form.

Abstract: A content addressable memory (CAM) protection circuit includes a memory cell having a read terminal for reading contents of the memory cell; a pass transistor coupled to the read terminal; and a latch having a first inverter with an input terminal and an output terminal coupled to the read terminal by the pass transistor and a second inverter with input and output terminals respectively coupled to the output and input terminals of the first inverter. The first inverter includes a pull-down transistor coupled between the output terminal of the first inverter and a first voltage reference and having a control terminal coupled to the input terminal of the latch and a pull-up transistor coupled between the output terminal of the first inverter and a second voltage reference and having a control terminal coupled to the input terminal of the latch.

Abstract: A device for generating a regulated DC voltage from a DC power supply voltage source includes a loop formed by a reference voltage generator powering an operational amplifier. The output of the operational amplifier powers the input to the reference voltage generator.

Abstract: A method of testing a DMOS power transistor that includes arranging a switch between low-voltage circuitry and the gate terminal of the DMOS power transistor, maintaining the switch in an open condition, applying a stress voltage to the gate terminal, testing the functionality of the DMOS power transistor, and, if the test has a positive outcome, short-circuiting the switch through zapping by fusing a normally-open fusible link. An integrated circuit device with DMOS transistor is provided that includes a gate terminal of the DMOS transistor coupled to a control element, a normally-open switch element coupled in series between the gate terminal and the control element and including two metallic regions with an insulating between them connected in parallel with the switch element and in series between the gate terminal and the control element.

Abstract: For an analysis of an electrical behaviour of a specific cell of a monolithically integrated circuit, a simulation model is used which is composed of a fine model part of the cell of interest and a coarse model part of the remainder of the integrated circuit.

Abstract: The invention relates to an electronic level shifter circuit for driving a high-voltage output stage. This output stage comprises a complementary pair of transistors connected between first and second supply voltage references, and at least one PMOS pull-up transistor connected in series with an NMOS pull-down transistor. An additional transistor is connected in parallel with the pull-up transistor, and the driver circuit has a first output connected to the control terminal of the pull-up transistor and a second output connected to the control terminal of the additional transistor.

Abstract: The present invention relates to an integrated circuit, at least one portion of which includes at least one group of standby cells for possible connection to said portion of the integrated circuit by replacement connections, the length of which cannot exceed a predetermined value. The inputs and outputs of the standby cells are connected to metal standby tracks being disposed on the circuit such that any node of the circuit portion is distant by at most said predetermined value from any point on the tracks.

Abstract: A primary circuit produces an internal resetting signal as a function of two input signals: an external resetting signal and a clock signal internal to the microprocessor. Depending on the characteristics of these two input signals, the internal resetting signal is generated according to a synchronous or an asynchronous mode. Generation of the internal resetting signal is delayed when the selection signal corresponds to the synchronous resetting mode.

Abstract: An integrated circuit and method are provided for sensing activity such as acceleration in a predetermined direction of movement. The integrated released beam sensor preferably includes a switch detecting circuit region and a sensor switching region connected to and positioned adjacent the switch detecting circuit region. The sensor switching region preferably includes a plurality of floating contacts positioned adjacent and lengthwise extending outwardly from said switch detecting circuit region for defining a plurality of released beams so that each of said plurality of released beams displaces in a predetermined direction responsive to acceleration. The plurality of released beams preferably includes at least two released beams lengthwise extending outwardly from the switch detecting circuit region to different predetermined lengths and at least two released beams lengthwise extending outwardly from the switch detecting circuit region to substantially the same predetermined lengths.

Abstract: The present invention relates to a method of manufacturing a MOS transistor, including the steps of delimiting, using a first resist mask N-type, drain and source implantation areas; removing the first mask and diffusing the implanted dopant; annealing, so that a thicker oxide forms above the source and drain regions than above the central gate insulation area; forming a polysilicon finger above the central gate insulation portion to form the gate of the MOS transistor; and performing a second source/drain implantation.