Abstract: The parameter J0 associated with the implementation of modular operations according to the Montgomery method is generated in an integrated circuit. J0 is encoded on Q*L bits such that J0=J0Q−1 . . . J00, wherein Q and L are integers. Loops are formed for the computation of the binary data elements J0j according to a known method, which is used for generating the sub-operands of L bits. A coprocessor is used for updating, by multiplication, of the value of a data element of Q*L bits of which the L least significant bits are used for the computation of the values of J0j.

Abstract: A process for selectively introducing a dopant into the bottom of a trench formed in a semiconductor material layer includes depositing a barrier layer by a process of deposition over the semiconductor material layer to form a deposited barrier layer. The deposited barrier layer has, over lateral walls and a bottom wall of the trench, a thickness which is lower than a nominal thickness of the deposited barrier layer over a planar surface of the semiconductor material layer. The method also including implanting a dopant using the deposited barrier layer as an implant mask.

Abstract: A method of identifying fingerprints, the method including the steps of: acquiring a test image formed by a number of test points characterized by different grey levels defining a test surface; determining significant points in the test image; and verifying the similarity between regions surrounding the significant points and corresponding regions of a reference image whose points present different grey levels defining a reference surface. The similarity between the regions is verified by computing the integral norm of portions of the test and reference surfaces; and the integral norm is computed using flash cells programmed with a threshold value correlated to the value of the grey levels in the reference region, by biasing the flash cells with a voltage value correlated to the grey level in the test region, and measuring the charge flowing through the flash cells.

Abstract: The charge injection circuit of this invention comprises at least one pair of floating gate MOS transistors having source and drain terminals which are coupled together and to an injection node, and at least one corresponding pair of generators of substantially step-like voltage signals having an initial value and a final value, and having outputs respectively coupled to the control terminals of said transistors. The signal generators are such that the initial value of a first of the signals is substantially the equal of the final value of a second of the signals, and that the final value of the first signal is substantially the equal of the initial value of the second signal.

Abstract: A method for testing whether an antenna circuit of a contactless chip card is defective. The antenna circuit is an inductive resonant circuit comprising a capacitor and an antenna coil. The antenna coil of the resonant circuit is excited by inductive coupling using a test coil wherein the excitation is then sharply interrupted. By detecting in the test coil a response signal generated by self-induction in the antenna coil of the resonant circuit and retransmitted to the test coil by inductive coupling, the response signal can be analyzed for determining whether a contactless chip card is defective. Application is well suited to the testing of antenna circuits for electronic portable devices working without contact, such as contactless chip cards, electronic labels, etc.

Abstract: A method and related circuit for adjusting the duration of a pulse synchronization signal for the reading phase of memory cells in electronic memory devices which are integrated on semiconductors are discussed. The pulse synchronization signal is produced by a pulse generator when it detects a logical state commutation on at least one input terminal of a plurality of addressing input terminals of the memory cells. The method produces a logical sum between the signal produced by the generator and a pulse signal having a predetermined duration. The logical sum is used to start up the reading phase.

Abstract: A voltage regulator is provided for limiting overcurrents when used with a plurality of loads, particularly in flash memories, which are connected between an output node of the regulator and a voltage reference by way of a plurality of switches. The voltage regulator includes at least one differential stage that has a non-inverting input terminal for a control voltage, and an inverting input terminal connected to the voltage reference and the output node of the regulator through a feedback network. There is an output terminal connected to the output node of the voltage regulator to produce an output reference voltage from a comparison of input voltages. In the voltage regulator is a main control transistor connected between a high-voltage reference and the output terminal of the regulator.

Abstract: A conveyor support for integrated circuits in an on-line oven, including a mechanism for driving and guiding the elements to be soldered while maintaining a lower surface of one of said elements in direct contact with a wall of the oven.

Abstract: A circuit technique to reduce the input capacitance line of a charge integrator is described. This approach is particularly tailored for embedded read-out circuits in solid-state integrated sensors. An integrated charge amplifier described herein includes a generic amplifier element and a high speed buffer which drives a metal shield placed underneath the input line. The metal shield therefore follows the potential of the input line and thereby reduces the capacitance between the input line and ground.

Abstract: The method described comprises the following steps: measuring, with a spectroscopic ellipsometer, the values of two quantities which are dependent on the thickness of the altered silicon layer and of a thin layer of silicon dioxide grown thereon with variations in the wavelength of the light of the measurement beam of the ellipsometer, obtaining from these measured values respective experimental curves representing the two quantities as functions of the wavelength, calculating the theoretical curves of the two quantities as functions of the wavelength considering the refractive indices and absorption coefficients of silicon dioxide and of the altered silicon as known parameters and the thickness of the altered silicon layer and the thickness of the thin silicon dioxide layer as unknowns, comparing the theoretical curves with the respective experimental curves in order to determine for which values of the unknowns the curves under comparison approximate to one another best, and extracting from the values dete

Abstract: A semiconductor device of the type having an integrated circuit with connection terminals connected to metal pads by connecting wires is provided. The integrated circuit includes a semiconductor substrate having a lower portion on top of which there is an upper layer that is more heavily doped than the lower portion. A first block and a second block are produced in the upper part of the substrate, and decoupling means are arranged in the vicinity of the first block. The decoupling means include at least one decoupling circuit that is connected to the lower portion of the substrate and to a ground connection pad, and the decoupling circuit has a minimum impedance at a predetermined frequency. In one preferred embodiment, the decoupling circuit includes an inductive-capacitive resonant circuit having a resonant frequency substantially equal to the predetermined frequency.

Abstract: A power MOSFET suitable for use in RF applications and a method for making the same is disclosed. The power MOSFET reduces the gate coverage of the drain region of the device in order to decrease the device gate to drain capacitance Cgd. A significant portion of the gate overlaying the drain region is eliminated by the removal of a portion of a polysilicon layer that is disposed over a substantial portion of the drain region that resides between the channel portions of the body regions of the device. The resulting open area, that is subsequently covered by an oxide layer, separates the polysilicon gate electrodes of the device. Finally, a metal layer is deposited over the entire structure to form the gate and source electrodes of the device.

Abstract: A regulation circuit for regulating an output voltage of a positive charge pump for an integrated circuit includes a comparison circuit receiving a reference voltage at an input, and delivering an enabling signal at an output to the positive charge pump. The regulation circuit further includes a first switching circuit controlled by a first control signal for the application of a first voltage level as a reference voltage when the integrated circuit is in an operational mode, and the application of a second voltage level as the reference voltage when the integrated circuit is in a standby mode.

Abstract: The invention provides a method of forming conductive members in an integrated circuit comprising the steps of depositing a first dielectric layer on a substrate; depositing a first conductive layer; depositing a second dielectric layer; forming cavities extending at least partially through the first dielectric layer; forming a second conductive layer on internal surfaces of the cavities; and electrolytically depositing another conductive material within the cavities.

Abstract: The invention relates to a pulse generator circuitry for timing a low-power memory device of a type associated to a memory matrix, including a plurality of word lines driven by a row decoder, and a plurality of bit lines sensed by sense amplifiers. The matrix includes at least a dummy row and at least one dummy column. A delay chain of the pulse generator is formed by the dummy datapath of the memory matrix. The dummy datapath being defined by at least on dummy row and at least one dummy column. The datapath operates prior to the operation of the normal row and column path of the matrix. In another embodiment disclosed, the row decoder comprises a dummy row enable portion at the intersection between the dummy row and the dummy column. The delay chain includes at least the dummy row enable portion, the dummy row and the dummy column.

Abstract: An apparatus and method for underfilling a silicon chip (16) to a substrate (12) by depositing an underfill dam (18) on the surface (20) of the substrate (12) prior to addition of the underfill material (14), is disclosed. A bead of underfill material (14) is provided on the substrate (12) about the periphery of the silicon chip (16), within the underfill dam (18). The underfill material (14) fills the gap (22) between the electrical contacts, the substrate (12) and the silicon chip (16) by capillary action and differential pressure created by a vacuum system (40).

Abstract: A method for starting a polyphase DC motor having a rotor. The position of the rotor is detected by initiating current in each of the phases of the motor and measuring a time period between the initiation of current in the coil and an instant when the current exceeds a threshold current. The phase in which the current reaches the threshold in the shortest amount of time is the phase closest to the position of the rotor. A phase closest to the position of the rotor is identified in each of an odd number of trials, and a starting phase is selected as the phase identified in the majority of trials. The motor is started by providing current to the starting phase.

Abstract: A MOS-gated power device includes a plurality of elementary functional units, each elementary functional unit including a body region of a first conductivity type formed in a semiconductor material layer of a second conductivity type having a first resistivity value. Under each body region a respective lightly doped region of the second conductivity type is provided having a second resistivity value higher than the first resistivity value.

Abstract: A modular arithmetic coprocessor comprises a circuit for the computation of an error correction parameter H=2x mod N associated with the Montgomery method. This computation circuit comprises a first register, a second register, and a first circuit for the series subtraction of either zero, N, twice N, or three times N from the contents of the first register. A multiplication circuit carries out a multiplication by four. A second circuit compares the result with N, twice N or three times N.

Abstract: Disclosed is a disc drive system that includes a digital signal processor for processing information sectors read from a CD media. The digital signal processor is configured to parse the information sectors into data frames and subcode frames. A data auto-start unit for triggering a data transfer to a buffer memory when a desired data frame is detected. A subcode auto-start unit for triggering a subcode transfer to the buffer memory when a desired subcode frame is detected. Preferably, the desired data frame and the desired subcode frame have a same MSF. The disc drive system further includes a buffer manager having a plurality of counters that are configured to track the number of data frames and the number of subcode frames being transferred to the buffer memory, and releasing a block including one of the data frames and one of the subcode frames when the counters indicate that the block is complete.