Abstract: A pair of equivalent controlled impedance buffers are connected in a push-pull configuration to the primary coil of a transformer. A pair of equivalent pre-drivers are connected to the pair of buffers. Each pre-driver receives a driver input signal and outputs a buffer input signal and a flyback compensation signal proportional thereto. Each buffer receives the buffer input signal generated from one of the pre-drivers for buffered output as a line driver signal to the primary coil. A flyback voltage effect is induced in each buffer due to the line driver signal applied to the primary coil by the other buffer. Each buffer further receives the flyback compensation signal generated from the other one of the pre-drivers, with the buffer operating to cancel the flyback voltage effect induced in that buffer by the line driver signal applied to the primary coil by the other buffer using the flyback compensation signal received from the other one of the pre-drivers.

Abstract: A comparator circuit includes a differential input stage, a second differential stage having a differential output, and an output stage transforming an output signal from the differential output of the second differential stage into an output signal having a logic level. The comparator further includes a common mode measuring stage. The common mode measuring stage includes a differential pair of input transistors and a differential pair of complementary transistors biased by respective current generators, and a current mirror summing the differential output currents of the two complementary transistors pairs into a single output current signal. A switching stage is controlled by the differential output nodes of the second differential stage. A common source node of the switch stage is coupled to the output of the common mode measuring stage and to the differential output nodes of the differential input stage.

Abstract: A method for recovering the original properties of a silicon oxide film that has suffered a high energy implantation of dopants in the underlying silicon substrate, includes a brief heat treatment without causing an excessive lateral diffusion in the silicon substrate of the implanted dopants. Heat treating in an oven at a temperature of 800° C. for few minutes per wafer, which was subjected to high energy implantation, makes it possible to recover etch rate characteristics that are practically similar to those of the original non-implanted silicon oxide.

Abstract: A fingertip-operated solid state capacitance switch detects a capacity change that is induced by the physical contact of an ungrounded fingertip to an external dielectric surface of the solid state switch. The input and output of a solid state signal-inverting amplifier are respectively connected to two relatively large and ungrounded capacitor plates that are associated with, but electrically isolated from, the switch's external dielectric surface. An ungrounded fingertip forms a third capacitor plate on the switch's external surface. The solid state amplifier detects the presence of a fingertip on the switch's external surface by way of a change in capacitance within a compound, three plate, capacitor that includes the two ungrounded capacitor plates and the ungrounded fingertip that is resident on the switch's external surface.

Abstract: A method of reducing power consumption of an electric circuit having a primary supply voltage and first and second circuit blocks is discussed. The method includes determining for the first circuit block an operation time for a first critical path of the first circuit block and determining for the second circuit block an operation time of a second critical path of the second circuit block. From those operation times, the method determines that the operation time of the first critical path is faster than the operation time of the second critical path. The method then creates a first supply voltage for the first circuit block that is less than the primary supply voltage in response to determining that the operation time of the first critical path is faster than the operation time of the second critical path.

Abstract: A step-up continuous-mode DC-to-DC converter with integrated current control, comprising a comparator for comparing a voltage signal output from the converter and a reference signal for generating an error signal and circuitry for generating a compensation ramp which generates a ramp signal which is added to a signal which is proportional to a current ramp that flows across the converter. The signal output from the comparator and the signal obtained from the sum are sent to an additional comparator, the output whereof, together with an oscillator signal, is used for driving a power transistor of the converter.

Abstract: A reference voltage generator that may be utilized in an integrated circuit such as a dynamic random access memory (DRAM) includes a voltage divider connected to a voltage supply and a feedback buffer amplifier. The voltage divider, which determines the reference voltage, supplies at least one voltage output signal to the feedback buffer amplifier under control of a feedback control signal supplied by the feedback buffer amplifier. In at least one embodiment, the reference voltage generator further includes a delay element coupled between the voltage divider and the feedback buffer amplifier in-line with the feedback control signal and a low impedance output buffer that receives the voltage output signal from the voltage divider and supplies the reference voltage at an output node. When the reference voltage generator is implemented within a dynamic random access memory, the reference voltage is supplied to the reference plates of bit storage capacitors within the memory cells.

Abstract: A process comprises the following operations: forming a structure of metal elements with functions of support and electrical connection, these metal elements having a high degree of surface finish; fixing a chip of semiconductor material, containing active parts and contact pads, to an area of a metal element of the structure acting as a support; electrically connecting the contact pads of the chip to predetermined metal elements of the structure acting as terminal conductors; and incorporating in plastic the chip of semiconductor material and part of the structure of metal elements. To improve the adhesion between the structure and the plastic, at least part of the surface of the metal elements is roughened by irradiation with a laser light beam.

Abstract: A flash compatible EEPROM device has a first flash matrix and a second matrix with EEPROM functionalities of substantially similar layout. Both are divided into blocks of cells formed in substrate regions isolated from one another. In the second matrix, the information is organized in pages each contained in a row of memory cells of one of the blocks of subdivision of the matrix. A hierarchic structure including a row decoder addresses the wordline of all the cells of a selected row of the block, co-operating with a column decoder in selecting single cells of the rows. A boosted voltage of a polarity opposite to the supply voltage of the device is applied during an erasing phase to a single wordline selected by the row decoder, to page-erase the information by applying a boosted voltage to the common source of all the cells of the block and to the isolated region of the substrate containing all the cells of the block.

Abstract: A method of fabricating an integrated circuit having an n-channel and a p-channel transistor is provided. The method includes forming LDD regions for the n-channel transistors self-aligned to the gate electrodes. A first oxide is then formed over the structure and the n-type silicon regions are implanting with a p+ type dopant through the first oxide to form the source and drain regions of the p-channel transistor. A second oxide is formed over structure. The two oxide layers are then etched to provide sidewall spacers, having an inner portion formed from the first oxide and an outer portion formed from the second oxide. The p-type silicon regions are implanted with an n+ type dopant to form the low resistivity regions of the n-channel transistor. The p+ implants in the source and drain of the p-channel transistor typically outdiffuse toward the gates during further thermal processing of the device.

Abstract: A dual supply device having a reference terminal, an input terminal for the application of a substantially constant input voltage relative to the reference terminal, a first output terminal for supplying a first supply voltage different from the input voltage, a second output terminal for supplying a second supply voltage substantially opposite to the first supply voltage a direct-current/direct-current converter connected between the input terminal and the first output terminal for converting the input voltage into the first supply voltage, and a capacitive translator connected between the first and second output terminals for translating the first supply voltage into the second supply voltage.

Abstract: The present invention utilizes a cache which stores various decoded instructions, or parcels, so that these parcels can be made available to the execution units without having to decode a microprocessor instruction, such as a CISC instruction, or the like. This increases performance by bypassing the fetch/decode pipeline stages on the front end of the microprocessor by using a parcel cache to store previously decoded instructions. The parcel cache is coupled to the microprocessor fetch/decode unit and can be searched during an instruction fetch cycle. This search of the parcel cache will occur in parallel with the search of the microprocessor instruction cache. When parcel(s) corresponding to the complex instruction being fetched are found in the parcel cache a hit occurs and the corresponding micro-ops are then sent to the execution units, bypassing the previous pipeline stages.

Abstract: The present invention relates to a circuit for controlling a fluorescent lamp, including circuitry that provides a low frequency alternating current to the fluorescent lamp, this circuitry being controlled by a controllable switched-mode current source operating at high frequency.

Abstract: The microcontroller accesses a battery of hidden registers used essentially in the field of emulation. The fact that there is a large number of hidden registers means that it is not possible to assign them an address by which they can be accessed directly. Since this battery of hidden registers has to be accessible by a host circuit and by a microprocessor, recourse is had to a method of indirect addressing by means of two peripheral control registers. A priority signal obliges the microprocessor to wait for the read and write resources to be released by the host circuit to perform these instructions.

Abstract: Process for manufacturing of an integrated structure including at least one circuitry transistor and at least one non-volatile EEPROM memory cell with relative selection transistor, including at least a first stage of growth and definition of a gate oxide layer on a silicon substrate, a second stage of definition of a tunnel oxide region in said gate oxide layer, a third stage of deposition and definition of a first polysilicon layer on said gate oxide layer and on said tunnel oxide region, a fourth stage of growth and definition of an intermediate dielectric layer on said first polysilicon layer, a fifth stage of selective etching and removal of said dielectric intermediate layer in a region for said circuitry transistor, a sixth stage of ionic implantation of a dopant with a first type of conductivity in order to introduce said dopant into a channel region for said circuitry transistor in order to adjust its threshold voltage, a seventh stage of deposition and definition of a second polysilicon layer on sai

Abstract: A device including an IGBT a formed on a chip of silicon consisting of a P type substrate with an N type epitaxial layer that contains a first P type region and a termination structure, and having a first P type termination region that surrounds the first region, a first electrode in contact with the first termination region, and a second electrode shaped in the form of a frame close to the edge of the chip and connected to a third electrode in contact with the bottom of the chip. A fourth electrode made in one piece with the first electrode is in contact with the first region. The termination structure also comprises a fifth electrode in contact with the epitaxial layer along a path parallel to the edge of the first termination region and connected to the second electrode and a second P type termination region that surrounds the fifth electrode and a sixth electrode, and which is in contact with the second termination region, connected to the first electrode.

Abstract: A hardware accelerator for a coding system for pictures includes an array of lines and columns of pixels, and calculates the variance of macroblocks of a digitized video image for a real-time coding of the current image together with the preceding and successive images, according to the MPEG-2 video algorithm. The architecture minimizes the silicon area needed for implementing the hardware accelerator for a cost-effective reduction on the CPU of the coding system. The use of a plurality of distinct filter/demultiplexers of known architectures is eliminated by conveying the incoming pixels to the respective input lines of distinct variance calculation paths by the use of a simple counter.

Abstract: A driver circuit includes a half-bridge output stage including two transistors with a common terminal for connection as the driver output to a coil of a DC motor. Two amplifiers drive the transistors in the push-pull operation and two capacitors are connected between the driver output and one input of a respective amplifier to form feedback loops for controlling the output slew-rate. Two current generators are selectively connected to an input of either of the amplifiers through respective pairs of switches. A commutation sequencer turns on and off the switches according to a commutation program. Comparators are connected to the drive output for detecting predetermined output voltage conditions and providing the commutation sequencer with signals for conditioning the commutation program as a function of the detected voltage conditions.

Abstract: Process for the manufacturing of a DMOS-technology transistor, providing for forming, over a semiconductor material layer of a first conductivity type, an insulated gate electrode, introducing in said semiconductor material layer a first dopant of a second conductivity type for forming at least one body region of a second conductivity type extending under the insulated gate electrode, and introducing in said at least one body region a second dopant of the first conductivity type for forming, inside said body region, at least one source region of the first conductivity type, said body region and said source region defining, under the insulated gate electrode, a channel region for the DMOS transistor, wherein said first dopant is aluminum. After the introduction of said first dopant and said second dopant, a single thermal diffusion process for simultaneously diffusing the first dopant and the second dopant is provided.

Abstract: A remanent, electrically programmable and erasable, memory device comprises of a MOS type transistor whose gate insulator contains charged mobile species is disclosed. The gate insulator is comprised transversely of a sandwich comprising at least five areas. Two intermediate areas have first band-gap values, and two endmost and a central areas have band gap values greater than the first values.