Abstract: A method and apparatus for decoding a multi-channel audio bitstream in which adaptive frequency domain downmixer (3) is used to downmix, according to long and shorter transform block length information (17), the decoded frequency coefficients of the multi-channel audio (12,13,14,15) such that the long and shorter transform block information is maintained separately within the mixed down left and right channels. In this way, the long and shorter transform block coefficients of the mixed down let and right channels can be inverse transformed adaptively (4,5,6,7) according to the long and shorter transform block information, and the results of the inverse transform of the long and short block of each the left and right channel added together (8,9) to form the total mixed down output of the left and right channel.

Abstract: A method of forming an insulated well in an upper portion of a silicon substrate, including the steps of providing a structure of silicon-on-insulator type including a silicon substrate, an insulating layer, and a thin single-crystal silicon layer; removing the insulating layer and the thin silicon layer outside locations where the insulated well is desired to be formed; growing an epitaxial layer; performing a planarization; and making a vertical insulating wall above the periphery of the maintained portion of the thin insulating layer.

Abstract: An electronic circuit generates a stable voltage signal for the polarization during a reading step of a UPROM redundancy cell incorporating at least one memory element of EPROM or Flash type, having at least one terminal to be polarized, and MOS transistors which connect such memory element to a low voltage power supply reference. The circuit includes a current mirror structure with a first control branch and a second output branch. The current mirror stricture includes a first series of MOS transistors (M2, M3, M4) in said first branch between the supply reference and a ground; and a second series of transistors (M5, M6, M7) in said second branch. The circuit also includes an input terminal connected to the gate terminal of a transistor of the first series of transistors and an output terminal corresponding to an interconnection node of the second series of transistors. The stable voltage is obtained through a current which passes through at least a pair of transistors of the second series.

Abstract: A semiconductor non-volatile memory device that includes memory cells and selection transistors. The memory cells each include a floating gate transistor having an active area, source and drain regions, a floating gate, and a control gate, and each of the floating gate transistors is serially coupled to one of the selection transistors. A contact to the control gate is located above the active area. In a preferred embodiment, the contact is substantially aligned with a central portion of the active area. A method for manufacturing a non-volatile memory device on a semiconductor substrate is also provided. According to the method, a poly1 layer is deposited, an interpoly dielectric layer is deposited above the poly1 layer, and a poly2 layer is deposited above the interpoly dielectric layer. A mask is provided to define the control gate, and a Self-Aligned poly2/interpoly/poly1 stack etching is used to define a gate stack structure that includes the control gate and the floating gate.

Abstract: The present invention relates to a method of cleaning of a semiconductor wafer covered with silicon oxide, topped with an aluminum layer in which patterns are formed by plasma etching of the aluminum, this etching causing the formation of a polymer containing, in particular, aluminum and carbon on the substantially vertical walls of the patterns, including rotating the wafer in its plane around its axis, in an enclosure under a controlled atmosphere, at ambient temperature, including the following steps rotating the wafer at a speed between 500 and 2000 rpm in an enclosure filled with nitrogen; sprinkling the wafer with water, substantially at the center of the wafer; introducing hydrofluoric acid during a determined cleaning time, while maintaining the sprinkling; and rinsing the wafer by continuing the sprinkling to remove any trace of hydrofluoric acid from the wafer, at the end of the cleaning time.

Abstract: A bus interface unit includes multiple pointer queues coupled to a random-access transaction buffer. The transaction buffer stores address and data information for each requested bus transaction, and the pointer queues store pointers to the transaction information stored in the transaction buffer. The bus interface unit uses the pointers to order the transactions stored in the random-access transaction buffer. In one preferred embodiment, one pointer queue is used to store pointers for order dependent transactions, and another pointer queue is used to store pointers for non-order dependent transactions. In some embodiments, when an issued transaction is deferred by its target, the deferred transaction's information is maintained in the transaction buffer. Additionally, a method is provided for storing address, data, and ordering information for requested bus transactions. The address and data information for requested transactions is stored as entries in a random-access buffer.

Abstract: A one-time programmable cell including an inverter providing a logic state according to the state of the cell; a fuse coupled between a first supply voltage and the inverter input; and a current source coupled between the fuse and a second supply voltage. The inverter is supplied from the second supply voltage through a first diode-connected transistor and the current source is formed of a second transistor controlled by the inverter output, this second transistor having a threshold voltage greater than that of the first transistor.

Abstract: A method for synchronously detecting servo information from a data disk includes reading servo information from a disk and passing the servo information signal through a Viterbi detector. The disk is encoded in a known data format from Gray code data to obtain a servo information signal, the encoded Gray code data being constrained to allow no more and no fewer than two “1” states to sequentially occur. The Viterbi detector is modified to eliminate state changes that do not occur within the constrained encoded Gray code data.

Abstract: A method and a circuit for switching a motor controller from pulse width modulation to linear control for a brush-less, sensor-less, poly-phase DC motor. The method includes steps of operating a drive circuit for a poly-phase direct current motor in a pulse width modulation mode and determining that a zero crossing will occur within a predetermined interval. The method also includes steps of enabling a bias current to a transconductance operational amplifier and changing an operating state of the drive circuit from the pulse width modulation mode to a linear mode. The method further includes steps of determining that the zero crossing has occurred, disabling the bias current to the transconductance operational amplifier and changing the operating state of the drive circuit from the linear mode to the pulse width modulation mode.

Abstract: An area-efficient low-pass, time-invariant, second-order reconstruction filter, particularly for current-driven digital-to-analog converters, including: a first resistor and a first capacitor which are parallel connected; an operational amplifier; a terminal of a second resistor which is connected to the inverting input of the operational amplifier; another terminal of the second resistor which is connected to a common node of the first resistor and the first capacitor; a second capacitor, which is ffeedback-connected between the output of the operational amplifier and the inverting input; and an additional pair of resistors which are arranged so as to provide feedback between the output and the inverting input, a current signal arriving from a digital-to-analog converter arranged upstream of the reconstruction filter being fed to a common node of the additional pair of resistors.

Abstract: A device for the generation of a drive signal phase-shifted with respect to an external synchronization signal includes a first digital phase-locked loop to give a reference signal, servo-linked to the external synchronization signal by a current phase among N phases of a high frequency signal. The device includes a second digital phase-locked loop including a measuring circuit to measure the position of an active edge of the drive signal or a derived signal that is delayed with respect to an active edge of the reference signal. The second phase-locked loop also includes a circuit to compute the phase shift to be made and a phase-shift circuit. The measurement circuit includes a circuit for the rough measurement of the position, controlled by a fixed phase of the high frequency signal independent of the present phase of locking in the first loop. The digital computation circuit accounts for this shift between the fixed phase and the present phase.

Abstract: A field-effect transistor and a method for its fabrication are described. The transistor includes a monocrystalline channel region extending from a monocrystalline body region of a semiconductor substrate. First and second source/drain regions laterally adjoin opposite sides of the channel region and are electrically isolated from the body region by an underlying first dielectric layer. The source/drain regions include both polycrystalline and monocrystalline semiconductor regions. A conductive gate electrode is formed over a second dielectric layer overlying the channel region. The transistor is formed by selectively oxidizing portions of a monocrystalline semiconductor substrate and then removing portions of the oxidized substrate. The resulting structure includes a body region of the substrate having overlying first and second oxide regions, with a protruding channel region extending from the body region between the oxide regions.

Abstract: The memory and method for reading include a synchronous multilevel non-volatile memory with cell addresses which define a pair of memory cells on different planes of the multilevel memory and plane addresses which define the plane on which the memory cell defined by a memory cell address is to be read. The memory and method include switching the plane address at a preset time interval after the switching of a memory address and at the highest possible switching frequency, and reading the content of a memory location, from the memory, which corresponds to the memory address on planes alternatively indicated by the switching of the plane address.

Abstract: The integrated microactuator has a stator and a rotor having a circular extension with radial arms which support electrodes extending in a substantially circumferential direction and interleaved with one another. For the manufacture, first a sacrificial region is formed on a silicon substrate; an epitaxial layer is then grown; the circuitry electronic components and the biasing conductive regions are formed; subsequently a portion of substrate beneath the sacrificial region is removed, forming an aperture extending through the entire substrate; the epitaxial layer is excavated to define and separate from one another the rotor and the stator, and finally the sacrificial region is removed to release the mobile structures from the remainder of the chip.

Abstract: The method is based on the use of a silicon carbide mask for removing a sacrificial region. In case of manufacture of integrated semiconductor material structures, the following steps are performed: forming a sacrificial region of silicon oxide on a substrate of semiconductor material; growing a pseudo-epitaxial layer; forming electronic circuit components; depositing a silicon carbide layer; defining photolithographically the silicon carbon layer so as to form an etching mask containing the topography of a microstructure to be formed; with the etching mask, forming trenches in the pseudo-epitaxial layer as far as the sacrificial region so as to laterally define the microstructure; and removing the sacrificial region through the trenches.

Abstract: The depth of a denuded layer with respect to a relatively defective bulk region of a monocrystalline semiconductor wafer is estimated in a nondestructive way. The depth is determined by measuring the lifetime or diffusion length of injected excess minority charge carriers on a surface of the wafer having such a denuded layer and on a different portion of the surface of the wafer from where the denuded layer has been previously stripped-off by lapping and/or etching. The depth is calculated through a best-fit procedure or through numerical processing of the measurement results on the basis of the diffusion equations of excess minority carriers.

Abstract: A lateral PNP bipolar electronic device integrated monolithically on a semiconductor substrate together with other NPN bipolar devices capable of being operated at high frequencies. The PNP device is incorporated to an electrically insulated multilayer structure which comprises a semiconductor substrate, doped for conductivity of the P-type, a first buried layer, doped for conductivity of the N-type to provide a base region, and a second layer, overlying the first and having conductivity of the N-type, to provide an active area distinguishable by a P-doped emitter region within the active area being located peripherally and oppositely from a P-doped collector region. The lateral PNP device can be operated at high frequencies with suitable collector current values and good amplification, to provide a superior figure of merit compared to that typical of conventional lateral PNP devices.

Abstract: A circuit and method to drive an H-bridge circuit are disclosed. The H-bridge circuit uses NMOS transistors for both the upper and lower sets of transistors. An inductive head is coupled between the terminals of the transistors. When a logic signal is received, one of the upper transistors is driven. The upper transistor selected to be driven is responsive to the logic signal. A corresponding lower transistor is also driven, forcing current through the inductive head in a first direction. The driving circuit for the lower transistors includes a programmable circuit structured to capacitively couple the output of the driving circuit to a pull-up voltage, thereby allowing the amount of current forced through the inductive head to be maximized for optimum data transfer. Within the programmable voltage boost circuit are several logic gates, each coupled to a capacitor of differing value.

Abstract: A voltage phase generator that generates a normal voltage phase, a negated normal voltage phase, a boosted voltage phase, and a negated boosted voltage phase. The voltage phase generator includes a first driver circuit that supplies the normal voltage phase to a first output node, and a second driver circuit that supplies the negated normal voltage phase to a second output node. The first and second driver circuits are driven by additional voltage phases that have a boosted voltage. In one preferred embodiment, each of the driver circuits includes a pull-up connected between a supply voltage and one of the output nodes, and a pull-down connected between ground and the one output node. Additionally, the present invention provides a voltage boosting circuit that includes a booster circuit and a voltage phase generator.

Abstract: An improved transistor package with superior stability to wave soldering, having a nickel oxide barrier strip formed on the surface of the leads.