Abstract: An MOS integrated circuit device with improved electrostatic protection capability includes high and low voltage rails for bringing externally-supplied power to points within the chip. Input bonding pads communicate input signals to the chip from external sources. Clamping circuitry connected to the input bonding pads clamps the input bonding pads to the low voltage rail during an electrostatic discharge event appearing on the input bonding pads. A receiver circuit is coupled to each input bonding pad. Each receiver circuit has a receiver input node, a receiver output node, and overvoltage-sensitive MOS circuitry between the input and output nodes. A conductor connects each input bonding pad to its receiver circuit. The conductor has a length greater than the distance between the input bonding pad and its receiver circuit. The conductor has an inductance sufficient to prevent high frequency components of ESD events received at an input bonding pad from reaching its receiver circuit.

Abstract: Process for fabricating a semiconductor non-volatile memory device arranged in rows and columns in a matrix structure, including a first step of forming active area's parallel lines delimited by field oxide lines using a Shallow Trench Isolation process, a second step of forming matrix rows which extend transversally to the active area lines, a third step of forming common source lines alternated between pairs of the matrix rows. The second step includes a first sub-step of forming first lines in a first polysilicon layer, along the active area lines, a second sub-step of forming an intermediate dielectric layer, a third sub-step of forming second lines in a second polysilicon layer for defining the matrix rows, a fourth sub-step of defining the intermediate dielectric layer, a fifth sub-step of etching the first polysilicon lines.

Abstract: An integrated circuit and method are provided for sensing activity such as acceleration in a predetermined direction. The integrated released beam sensor preferably includes a switch detecting circuit region and a sensor switching region connected to and positioned adjacent the switch detecting circuit region. The sensor switching region preferably includes a fixed contact layer, remaining portions of a sacrificial layer on the fixed contact layer, and a floating contact on the remaining portions of the sacrificial layer and having only portions thereof directly overlying the fixed contact layer and in spaced relation therefrom in a normally open position and extending lengthwise generally transverse to the predetermined direction so that the floating contact contacts the fixed contact layer responsive to acceleration in the predetermined direction. The floating contact is preferably a released beam which is released by opening a window or removing unwanted portions of the sacrificial layer.

Abstract: A voltage regulation device is provided for receiving a voltage at an input node and supplying a regulated voltage to electronic circuitry at an output node. The device includes a switching circuit that is coupled between the input node and the output node, and a control circuit that is coupled to the switching circuit. When the voltage level at the output node is below a threshold voltage, the control circuit controls the switching circuit so as to substantially short-circuit the input node and the output node. On the other hand, when the voltage level at the output node is not below the threshold voltage, the control circuit controls the switching circuit so as to substantially isolate the input node from the output node. In a preferred embodiment, the switching circuit includes an NMOS transistor, and the control circuit includes a differential amplifier that supplies a control signal to the gate of the NMOS transistor. A smart card containing a voltage regulation device is also provided.

Abstract: An electronic switch in integrated circuit from includes a first n-channel MOS transistor and a second n-channel MOS transistor with respective source-drain paths in series between an input terminal and an output terminal, and a third n-channel MOS transistor connected between a connection node between the first and second transistors and a supply terminal. The gate electrodes of the first and second transistors are connected together to a first control terminal and the gate electrode of the third transistor is connected to a second control terminal of the electronic switch. The first and third transistors are formed in a first p-well and the second transistor is formed in a second p-well, insulated from the first. A circuit branch which is identical, but provided by p-channel MOS transistors is also provided between the input and output terminals.

Abstract: A frequency translator is usable in a switching DC-DC converter of the type operating as a voltage regulator and as a battery charger. The frequency translator receives at inputs a division voltage (VFB) proportional to a present value of the output voltage (VOUT) of the DC-DC converter, a reference voltage (VREF) correlated to a nominal value of the output voltage (VOUT), and a limiting signal (VL) indicative of a normal operation or of current limitation operation of the DC-DC converter, and supplies at an output a bias current (IBIAS) which is supplied to an input of an oscillator supplying at an output a comparison signal (VC) presenting a periodic pattern with a frequency which is correlated to the bias current (IBIAS).

Abstract: A device for two-way digital transmission on a bus having at least one two-way line. The device includes a first pulling device for pulling a first section of the line to a first logic level, a second pulling device for pulling a second section of the line to the first logic level, and at least one two-way repeater that is connected between the first section and the second section. The repeater includes a third pulling device for pulling the first section of the line to a second logic level, a fourth pulling device for pulling the second section of the line to the second logic level, and a logic circuit that prevents the third and fourth pulling devices from being simultaneously active. In one preferred embodiment, at least one electronic circuit is connected to the first section of the line and at least one other electronic circuit is connected to the second section of the line.

Abstract: A capacitor integrated on a silicon substrate includes a first electrode made of highly doped polysilicon, a thin silicon oxide layer, a second electrode made of polysilicon and a silicide layer covering the second electrode. The second electrode has a high dopant concentration at its interface with the silicon oxide layer and a low or medium dopant concentration at its interface with the silicide layer.

Abstract: A device and method for the reading of cells of an EEPROM is provided. The device includes at least one reference cell and one circuit for comparison between a current flowing into the reference cell and a current flowing in a cell selected in read mode. The reference cell is in a programmed state. The programming of the reference cell is done after the control reading and during the integrated circuit power-on reset phase, activated by the powering on of the integrated circuit.

Abstract: The present invention relates to a DRAM circuit including a plurality of memory cells organized in an array, including switches for associating with each end of each column of the array at least two latches controlled independently from each other to store data written into or read from the considered column.

Abstract: A differential decoder has a wide output dynamic range and reduced area consumption. The decoder includes a plurality of inputs which are correlated to a plurality of output lines. The output lines are driven by respective NPN type bipolar transistors which are connected to the output lines by their emitters while the input signals are fed to their bases. The decoder also includes a plurality of additional output lines which are complementary to the output lines and another plurality of NPN type bipolar transistors which are suitable to drive the additional output lines. The additional bipolar transistors are connected to the additional output lines through their emitter terminals, and are connected to the base and collector terminals of the bipolar transistors that drive the output lines, through their base and collector terminals.

Abstract: The present invention relates to a switchable d.c. voltage regulation circuit having an input terminal, an output terminal, a reference terminal, and a control terminal, including a gate turn-off thyristor, the main terminals of which are connected to the input terminal and to the output terminal, respectively; a resistor connected between the input terminal and the cathode gate of the thyristor; a transistor, the main terminals of which are connected to the cathode gate of the thyristor and to the reference terminal, respectively; and an avalanche diode connected between the output terminal and the base of the transistor.

Abstract: An algorithm based on a pre-analysis implements an efficient constant bit-rate control with a reduced requirement on a buffer memory capacity. The pre-analysis is on at least one slice (GOS) of the current whole picture, and/or on a mix of information on the pre-analysis of a slice of the preceding picture and on the actual encoding data of the preceding whole picture. The pre-analysis may be carried out by precoding the GOS with a constant reference quantizer or by entropy computation. The local control of the bit-rate is implemented by an integrative-proportional controller.

Abstract: The bond between a flip chip integrated circuit and a substrate is subject to mechanical stress from thermal cycles. This problem is exaggerated when the substrate has a rate of thermal expansion which is appreciably different from that of silicon. This problem is further exaggerated when the IC has a large footprint because it will experience a larger absolute expansion. A solution is proposed to this problem which involves creating an anchoring point. The anchoring point can be in either the IC or the substrate and can be a through-hole or a surface indentation such as a groove or a cutout. The anchoring point is filled with the underfill material during the underfill process. The anchoring point thus provides additional mechanical strength to the bond between the IC and the substrate.

Abstract: Relatively low currents are monitored through an integrated DMOS power transistor in a low-side driver configuration. A feedback circuit is responsive to the voltage applied to a gate of the DMOS power transistor to limit the minimum value to which the drain-source voltage may drop to keep it sufficiently high, and to allow a reliable monitoring of the current through the power transistor, even at relatively low levels. This is performed by increasing the conduction resistance of the power transistor at low current levels.

Abstract: An electronic memory circuit comprises a matrix of EEPROM memory cells. Each memory cell includes a MOS floating gate transistor and a selection transistor. The matrix includes a plurality of rows and columns, with each row being provided with a word line and each column comprising a bit line organized in line groups so as to group the matrix cells in bytes, each of which has an associated control gate line. A pair of cells have a common source region, and each cell symmetrically provided with respect to this common source region has a common control gate region.

Abstract: The device described permits selection between two design options of an integrated circuit by causing a corresponding circuit unit of the integrated circuit to adopt one of two possible different operative states. It comprises an inverter, of which the output terminal is connected to the control terminal of the circuit unit and the input terminal is connected to a first supply terminal by means of a conductor which can be broken by means outside the integrated circuit, and to the second supply terminal by means of a capacitor in parallel with a diode connected for reverse conduction. The device described does not require control signals, takes up a very small area, has practically zero consumption, and can be formed in unlimited numbers on the same integrated circuit.

Abstract: A power rising electronic device receives an input current and supplies an output current that is a function of a power of the input current having a relative whole-number exponent. The power rising electronic device includes a plurality of diodes equal to an absolute value of the relative whole-number exponent. The plurality of diodes are connected in series with one another to produce from the input current an input voltage that is a logarithmic function of a power of the input current. The electronic device further includes an output junction element, and a circuit for applying a voltage that is a function of the input voltage to the output junction element for producing a current that is an exponential function of the voltage applied thereto. The output current of the power rising electronic device is derived from the current produced in the output junction element.

Abstract: The present invention provides a method for minimizing voids in a plug. The process begins by forming a conformal barrier layer within the hole and then forming a metal plug within the hole. Thereafter, a cap layer is formed over the metal plug in which the cap layer has a lower thermal expansion coefficient than the metal plug. The hole is heated such that the metal in the hole flows to eliminate the void as a result of the compressive stress generated by the cap layer on the metal plug.

Abstract: A method for testing decoding circuits in a memory including a matrix of storage cells includes writing the same first word in all the storage cells, and then writing second words in the matrix such that each row and each column has at least one stored second word. The second words are different from the first words. If several second words are written in the same row or in the same column, then the second words are different from one another. Reading all the words in the memory permits verification of the integrity of the decoding circuits, and reduces the testing time of the memory.