Abstract: An MOS integrated circuit device with improved electrostatic protection capability includes high and low voltage rails for bringing externally-supplied power to points within the chip. Input bonding pads communicate input signals to the chip from external sources. Clamping circuitry connected to the input bonding pads clamps the input bonding pads to the low voltage rail during an electrostatic discharge event appearing on the input bonding pads. A receiver circuit is coupled to each input bonding pad. Each receiver circuit has a receiver input node, a receiver output node, and overvoltage-sensitive MOS circuitry between the input and output nodes. A conductor connects each input bonding pad to its receiver circuit. The conductor has a length greater than the distance between the input bonding pad and its receiver circuit. The conductor has an inductance sufficient to prevent high frequency components of ESD events received at an input bonding pad from reaching its receiver circuit.

Abstract: The reading circuit comprises a current source, which, via a current reflection circuit, supplies a constant predetermined current to a cell to be read, an operational amplifier with a non-inverting input connected to the drain terminal of the cell, and an output connected to the gate terminal of the cell. The source terminal of the cell is connected to ground. Thereby the output voltage of the operational amplifier supplies directly (at the set current) the threshold voltage of the cell, and the drain terminal of the cell is biased to a positive voltage.

Abstract: A system for processing a floating point instruction includes a stack, virtual registers, a stack pointer pointing to one of the virtual registers as top of stack, physical registers, and a reference table mapping the virtual registers to the physical registers, entries of the reference table pointing to physical register locations. An instruction unit generates a plurality of instructions, and a decode unit having a plurality of decoders receives the plurality of instructions from the instruction unit, respectively. The decode unit decodes the plurality of instructions and determines whether any one of the instructions contains a floating point instruction including a floating point exchange instruction. A logic unit is coupled to the reference table and includes a plurality of logic devices coupled to the plurality of decoders in the decode unit, respectively.

Abstract: A neural network including a number of synaptic weighting elements, and a neuron stage; each of the synaptic weighting elements having a respective synaptic input connection supplied with a respective input signal; and the neuron stage having inputs connected to the synaptic weighting elements, and being connected to an output of the neural network supplying a digital output signal. The accumulated weighted inputs are represented as conductances, and a conductance-mode neuron is used to apply nonlinearity and produce an output. The synaptic weighting elements are formed by memory cells programmable to different threshold voltage levels, so that each presents a respective programmable conductance; and the neuron stage provides for measuring conductance on the basis of the current through the memory cells, and for generating a binary output signal on the basis of the total conductance of the synaptic elements.

Abstract: A circuit for charging a capacitance using an LDMOS integrated transistor controlled in a manner to emulate a high voltage charging diode of the capacitance. The circuit avoids the switch-on of parasitic bipolar transistors of the LDMOS structure during transient states. The circuit includes a number of junctions directly biased between a source node and a body node of the LDMOS transistor, a current generator referred to a ground of the circuit, at least one switch between the source and a first junction of a chain of directly biased junctions, and a limiting resistor connected between the body and the current generator referred to ground. The switch is open during a charging phase of the capacitance and is closed when the charging voltage of the capacitance exceeds a preestablished threshold responsive to a control signal.

Abstract: A method of stress testing a DRAM such that higher voltages of up to the supply voltage VDD may be applied to the oxide of memory cell capacitors. The DRAM is driven into a stress test mode when the sense amplifiers have been isolated, the precharge voltage and the half bitlines have been grounded, and the word line boost circuitry has been disabled or set to operate at a lower voltage level. These conditions allow the memory cell capacitors, isolated from the sense amplifiers and the word line boost circuitry, to be stress tested independently at a lower power supply and word line voltage levels than are used to stress test conventional DRAMs. The memory cell oxide stresses are applied at room temperature, in wafer form, in seconds instead of hours, and before the configuration of redundancy elements. The inventive method permits the critical burn-in VDD value to be chosen so as to optimize burn-in of the memory cell capacitors and peripheral CMOS circuitry.

Abstract: A voltage regulator which has two regulation circuits and a comparator for controlling the two regulation circuits is disclosed. The input of the comparator is connected to a power supply voltage such that the output of the comparator changes states when the power supply voltage reaches a predetermined voltage of around 8 volts. The first regulation circuit is enabled to provide the Vcc from the battery voltage until the power supply voltage reaches around 8 volts which is when the comparator changes states. At that point, the first regulation is disabled and the second regulation circuit is enabled to provide the Vcc voltage from the power supply voltage. Since the power supply voltage never reaches the load dump high voltages, the second pass transistors never gets exposed to a high voltage condition. Also, the first transistor can withstand higher voltages since its base is grounded.

Abstract: This invention is a method for boosting the voltage level of a wordline in a DRAM having bitlines, sense amplifiers, isolation devices, bitline loads, an X decoder device and a Y select device. In the preferred method, when the wordline level reaches VDD, the decoder is disabled causing the wordline to stay at the VDD level. The sensing amplifier is also caused to be isolated so as to allow the wordline voltage to track the bitline voltage through capacitive coupling across the access MOSFET of the memory cell being read or written to. As a result, the wordline voltage is increased to a supervoltage as the bitline voltage increases. After the supervoltage is reached on the wordline, the sensing amplifier is connected causing feedback from the amplifier to drive the wordline voltage toward the VDD level and the disabled bit toward GND during this time. At the end of the wordline clock signal, the voltage is at GND and each of the bitlines are returned to their neutral mid-voltage level.

Abstract: Switching circuit that receives a supply voltage, a reference voltage, a line adapted to carry a negative voltage and a control signal, the switching circuit capable of providing at an output a voltage alternatively equal to the reference voltage or to the voltage of the line in response to the control signal. The circuit includes a first MOSFET with a first electrode operationally connected to the line, a second electrode operationally connected to the output, and a control electrode, a second MOSFET with a first electrode operationally connected to the reference voltage, a second electrode operationally connected to the output, and a control electrode, and driving circuitry adapted to bring the control electrodes of the first and second MOSFETs respectively to the supply voltage and to the voltage of the line or, alternatively, to the voltage of the line and to the supply voltage, in response to the control signal.

Abstract: An analog-signal to square-wave-signal reshaping system for threshold-dependent reshaping of an analog input signal to a square wave signal; comprising an offset-inflicted reshaping circuit having a signal input adapted to be fed with the analog input signal, a reference input adapted to be fed with a reference voltage determining the reshaping threshold, and a signal output from which the square wave signal is available; an offset storage circuit connected to the signal input of the reshaping circuit and adapted to store a charging voltage corresponding to the offset voltage of the reshaping circuit, with this charging voltage being adapted to be superimposed on the analog input signal for offset compensation; a controllable switch circuit which in a first switching state takes no influence on the reshaping function of the reshaping circuit and, for the purpose of offset compensation, in a second switching state interrupts the reshaping operation of reshaping circuit and effects charging of the offset storag

Abstract: A contactless chip card, receiving binary data transmitted by radio frequency, includes a demodulator for the binary data. The demodulator includes a circuit for the detection of the transmitted signals, a rectifier circuit, a bandpass filter, two comparators and a memory circuit. The bandpass filter provides a low-frequency signal used as a reference for the two comparators and a high-frequency signal that is compared with the references varying with the low frequency signal. As a result, the demodulation is independent of the mean level of the received signal.

Abstract: A invention provides a transformer for use in integrated circuits, comprising four layers of conductive lines, separated from each other by first, second and third insulating layers. First conductive vias traverse the second insulating layer to connect said second and third pluralities of conducting lines, to form a first winding. Second conductive vias traverse the first, second and third insulating layers to connect said first and fourth pluralities of conducting lines to form a second winding, about and approximately concentric with said first winding.

Abstract: A read/write head in a recording and retrieval system and method of operating the read/write head are disclosed. The read/write head contains two inductive sections coupled to a switch. During a read operation, the switch is open connecting the sections in series and maximizing the inductance of the read/write head to produce a better read operation. During a write operation the switch is closed connecting the sections are in parallel to reduce the inductance of the read/write head to produce a better write operation. The switch is controlled by the R/W.sub.-- signal of the recording and retrieval system. The inductance of the inductive sections can be modified to optimize the read and write operations.

Abstract: A method of reducing the memory required for decompression of a compressed frame by storing frames in a compressed format using DCT compression and decoders for implementing such a method are disclosed. The decoder is coupled to a memory where the frame can be stored. The decoder includes a decoder module having a parser, a block decoder module and a motion compensation engine. The decoder module is coupled to a DCT encoder module, which has an output coupled to the memory. The decoder also includes a stored DCT decoder module, which has an input coupled to the memory, a first output coupled to the motion compensation module and a second output that functions as an output of the decoder. In operation, any prediction frames needed for motion compensation decompression of the compressed frame are decompressed in the stored DCT decoder module. The compressed frame is decompressed in the decoder module to obtain a decompressed frame.

Abstract: To manufacture integrated semiconductor devices comprising chemoresistive gas microsensors, a semiconductor material body is first formed, on the semiconductor material body are successively formed, reciprocally superimposed, a sacrificial region of metallic material, formed at the same time and on the same level as metallic connection regions for the sensor, a heater element, electrically and physically separated from the sacrificial region and a gas sensitive element, electrically and physically separated from the heater element; openings are formed laterally with respect to the heater element and to the gas sensitive element, which extend as far as the sacrificial region and through which the sacrificial region is removed at the end of the manufacturing process.

Abstract: A method of a storing a picture in a memory such that bandwidth can be reduced when retrieving an array portion of the picture from the memory, and a memory architecture are disclosed. The memory is subdivided into a plurality of words for storing a picture having rows and columns. The picture is partitioned into two or more stripes each having a predetermined number of columns. The number of bytes in one row of one stripe is equal to the number of bytes in one word, for storing the data in one row of a stripe in one word. For the case of progressive video sequences or images the memory is organized in frame structure. For the case of interlaced video sequences or images, the memory is organized in field structure. For a frame picture to be stored in a frame organized memory or a field picture to be stored in a field organized memory, the data in the first row of one of the stripes is stored in a first word.

Abstract: The invention relates to a driving circuit for row decoding which is also useful in non-volatile memory devices of the multi-level Flash type and the multi-level EPROM type and allows the overall capacitive loads as seen from the program voltage generator and the read/verify voltage generator, to be drastically reduced without involving segmentation of the decoding circuit.

Abstract: An electric circuit having a switchable feedback branch switchable between a first feedback state, in which the circuit arrangement has a frequency response that is stable with respect to an oscillation tendency, and a second feedback state, in which the circuit arrangement has a frequency response that is unstable with respect to an oscillation tendency. The circuit includes a switchable frequency response compensation circuit which during the first feedback state of the feedback branch can be controlled to an ineffective state and during the second feedback state of the feedback branch can be controlled to an effective state, and in the effective state causes such compensation of the frequency response of the circuit arrangement in the second feedback state that the circuit arrangement in the second feedback state remains stable with respect to an oscillation tendency.

Abstract: A level shift circuit for a voltage input signal (S, SN) presenting at least a first and a second high-voltage levels, the circuit comprising two parallel branches, each formed by a current modulator and a signal converter. The current modulators are supplied with two signals in phase opposition to each other, and generate current signals whose value depends on the level of the respective input signal; and the signal converters convert the current signals into ground-related voltage signals. The signal converters together form a single-ended differential circuit, the output of which therefore presents a low-voltage digital signal which can be processed by normal digital circuits and is unaffected by noise or variations in supply voltage.

Abstract: The method described provides for the formation of an implantation mask of polycrystalline silicon comprising strips for providing the gate electrodes of the MOS transistors and portions defining openings for the formation of resistors. The method further includes low-dose ionic implantation through the implantation mask to form pairs of regions at the sides of the gate strips and resistive regions through the openings, the formation of an insulating layer on the entire structure thus produced, and anisotropic etching of the insulating layer so as to uncover the areas of the substrate not covered by the polycrystalline silicon mask, but leaving a residue of insulating material along the edges of the gate strips.