Abstract: Electro-static-discharge (ESD) protection circuits are supplied for inhibiting the destruction of buffers, drivers, logic and memory cells in Metal-Oxide-Semiconductor (MOS) devices such as a CMOS device including Static-Random-Access-Memory (SRAM). This is accomplished by tiering diodes adjacent the input of the chip and in certain specific areas internally of the chip (e.g. power supplies etc.) providing bidirectional diode protection from over-voltage.

Abstract: A mask is used for lightly doped drain and halo implants in an integrated circuit device. The mask exposes only portions of the substrate adjacent to field effect transistor gate electrodes. Since the halo implant is made only near the transistor channels, where it performs a useful function, adequate device reliability and performance is obtained. Since the halo implant is masked from those portions of the active regions for which it is not necessary, active region junction capacitances are lowered. Such lowered capacitances result in an improved transistor switching speed. The mask used to define the lightly doped drain and halo implant region can be easily formed from a straight forward combination of already existing gate and active area geometries.

Abstract: An integrated circuit package for direct mounting of an integrated circuit die to a printed circuit board is disclosed. The integrated circuit die includes a silicon sensor that detects changes in external variables, such as providing an image of a human fingerprint. The integrated circuit die has wire bond pads formed along only one side thereof to provide maximum exposure of the top surface area of the silicon sensor. The die is affixed to the printed circuit board and an adhesive surface coating, such as epoxy, is applied to the die and the printed circuit board for sealing the die thereto. The adhesive surface coating is formed from a first bead applied to the printed circuit board to cover at least the ends of the wires bonded to the board and a second bead applied to the first bead and the die to enclose the sides of the die and partially overlap the wire band pads and wires on top surface thereof.

Abstract: An integrated circuit and method are provided for sensing activity such as acceleration in a predetermined direction. The integrated released beam sensor preferably includes a switch detecting circuit region and a sensor switching region connected to and positioned adjacent the switch detecting circuit region. The sensor switching region preferably includes a fixed contact layer, remaining portions of a sacrificial layer on the fixed contact layer, and a floating contact on the remaining portions of the sacrificial layer and having only portions thereof directly overlying the fixed contact layer and in spaced relation therefrom in a normally open position and extending lengthwise generally transverse to the predetermined direction so that the floating contact contacts the fixed contact layer responsive to acceleration in the predetermined direction. The floating contact is preferably a released beam which is released by opening a window or removing unwanted portions of the sacrificial layer.

Abstract: A method is provided for forming a landing pad of a semiconductor integrated circuit, and an integrated circuit formed according to the same. A plurality of conductive regions are formed over a substrate. A polysilicon landing pad is formed over at least one of the plurality of conductive regions. After the polysilicon is patterned and etched to form the landing pad, tungsten is then selectively deposited over the polysilicon to form a composite polysilicon/tungsten landing pad which is a good etch stop, a good barrier to aluminum/silicon interdiffusion and a good conductor.

Abstract: Electro-static-discharge (ESD) protection circuits are supplied for inhibiting the destruction of buffers, drivers, logic and memory cells in Metal-Oxide-Semiconductor (MOS) devices such as a CMOS device including Static-Random-Access-Memory (SRAM). This is accomplished by tiering diodes adjacent the input of the chip and in certain specific areas internally of the chip (e.g. power supplies etc.) providing bidirectional diode protection from over-voltage.

Abstract: A dual gain amplifier provides separate gains so that the amplifier's input characteristics are unaffected by the gain selected. The dual gain amplifier comprises a first input amplifier and a third amplifier connected in cascade, and a second input amplifier and a fourth amplifier connected in cascade. A first LC circuit is connected in parallel to a second LC circuit which are both connected to the third amplifier. Likewise, a third LC circuit is connected in parallel to a fourth LC circuit which are connected to the fourth amplifier. The first and third LC circuits have a first quality factor and the second and fourth LC circuits have a second quality factor. The dual gain amplifier switches from a first state in which only the first and third LC circuits conduct to a second state in which all four LC circuits conduct.

Abstract: A mixed mode PWM/Linear driving system for at least one inductive-resistive (L-R) actuator as a function of operating conditions thereof includes a first full bridge power stage including four power switching devices arranged in pairs for being driven in phase opposition. The system also includes a pulse width modulation (PWM) converter for producing a PWM signal directly driving the first full bridge power stage during a PWM mode operating phase. A second full bridge power stage also comprises four power switching devices of different electrical characteristics from the power switching devices of the first full bridge power stage. The system further includes a pair of amplifiers connected to respective pairs of power switching devices of the second full bridge power stage for driving same in phase opposition during a linear mode operating phase. A switch is provided for switching between the PWM mode operating phase and the linear mode operating phase.

Abstract: An improved processing technique results in a structure which maximizes contact area by eliminating a sidewall spacer used to form LDD regions. A sacrificial spacer is provided during processing to form the LDD regions, and is then removed prior to further processing of the device. A sidewall spacer is then formed in a self-aligned contact from a later deposited oxide layer used as an interlevel dielectric. This leaves only a single oxide sidewall spacer alongside the gate electrode, maximizing the surface area available for the self-aligned contact itself.

Abstract: A process for the formation of a device edge morphological structure for protecting and sealing peripherally an electronic circuit integrated in a major surface of a substrate of semiconductor material includes formation above an intermediate process structure of a dielectric multilayer comprising a layer of amorphous planarizing material. The process also includes the partial removal of the dielectric multilayer so as to create at least one peripheral termination of the multilayer in the device edge morphological structure. Removal of the dielectric multilayer requires that the peripheral termination thereof be located in a zone of the intermediate process structure relatively higher than the level of the major surface, if compared with adjacent zones of the intermediate structure itself at least internally toward the circuit and in so far as to the device edge morphological structure.

Abstract: A method of forming an isolation region in an integrated circuit and an integrated circuit formed thereby. A method preferably includes forming at least one trench in a semiconductor substrate, forming an insulation layer of material in the at least one trench and on peripheral regions of the at least one trench of the semiconductor substrate, forming a sacrificial layer of material on the insulation layer having a different polishing rate than the insulation layer, and polishing the layer having the different polishing rate and portions of the insulation layer so that the sacrificial layer having the different polishing rate and portions of the insulation layer are removed, so that other portions of the insulation layer remain in the at least one trench of the substrate, and so that the upper surface of the at least one trench and the peripheral regions thereof in combination provide a substantially planar surface.

Abstract: A device for the selection of address words each having n bit locations and serving for addressing m different receiving locations of a digital communication module, in at least one of the receiving locations, including a digital acceptance module through which address words can be selected. The device has an address word segmenting module through which each address word received by the receiving location can be subdivided into s address word segments with b segment bit locations each, wherein b=n/s and n is an integral multiple of s. The device further has z digital segment filters whose inputs can each be fed with an address word segment, with each segment filter having the function of examining one address word segment each with respect to conformity with a predetermined segment bit pattern, and a filter output signal being available at the output of the respective segment filter, which in accordance with the examination result is either a conformity signal or a non-conformity signal.

Abstract: An electrical switching device including a switch having a control terminal, a control circuit coupled between a first voltage source terminal and a second voltage source terminal and a control signal input coupled to receive a binary switching control signal.

Abstract: The present invention relates to a radio receiver, particularly to a receiver for use in single-frequency applications, such as GPS, and to a frequency generator, which may be used in such a radio receiver, or elsewhere. The frequency generator comprises a tuned circuit connected between the emitter of the transistor and ground, such that a voltage signal at the basic frequency appears on the emitter terminal of the transistor. This arrangement has the advantage that the two frequencies appear on separate ports, and provides a radio receiver including radio receiver circuitry for connection to digital signal processing circuitry, reducing the complexity of the overall circuit. Additionally, there is a radio receiver wherein separate first and second local oscillator signals are generated from the terminal of s single transistor, avoiding the need for cascade multiplication stages, again reducing the size and complexity of the overall circuit.

Abstract: The row decoder includes a predecoding stage supplied with row addresses and generating predecoding signals; and a final decoding stage, which, on the basis of the predecoding signals, drives the individual rows in the array. The predecoding stage includes a number of predecoding circuits presenting two parallel signal paths: a low-voltage path used in read mode, and a high-voltage path used in programming mode. A CMOS switch separates the two paths, is driven by high voltage via a voltage shifter in programming mode, and, being formed at predecoding level, involves no integration problems.

Abstract: A method and apparatus for testing a random access memory device, such as a dynamic random access memory device embedded within an integrated circuit chip. The apparatus includes one or more rows of transistors, each of which is connected to a bit line pair of the memory device and to a data line. Data is placed onto the bit lines by driving the data line to a predetermined voltage level and turning on the transistors in the transistor row. Data placed on the bit lines forms a test pattern that may be subsequently written into any row of memory cells. By directly controlling the bit lines of the memory device in this way, test patterns may be quickly and easily stored in the memory device for functional verification thereof.

Abstract: The present invention relates to the use of a conventional MOS transistor as a memory point in which, during programming, the well of the MOS transistor is connected to a reference potential, the drain and the source are connected to a current source adapted to bias the drain and source junctions in reverse and in avalanche so that the space charge region extends along the entire channel length, the gate is set to the reference potential if the memory point does not have to be programmed and to a distinct potential if the memory point has to be programmed; and during the reading, circuitry is provided to detect a high or low impedance state between the gate and the well.

Abstract: A MOS integrated multistage differential single ended amplifier circuit includes an input circuit generating two differential current outputs, and an output circuit. The output circuit includes a current mirror circuit including two current generators and two branches into which are injected two currents each corresponding to a difference between a bias current generated by a respective current generator and a respective differential current output of said input circuit. The output circuit also includes two diode-connected MOS transistors forming respective current mirrors with the two current generators through which the differential output currents are respectively forced, mirroring the differential output currents on the current generators, respectively, and with a certain mirroring ratio. Two voltage reference MOS transistors are also provided having gates connected to injection nodes of the differential output currents on the diode-connected MOS transistors.

Abstract: This invention relates to a voltage comparator with an input for an analog signal and an output for a digital signal, comprising an inverter which has an input coupled to the comparator input and an output coupled to the comparator output, and comprising at least two MOS transistors coupled to each other, at least one of the two MOS transistors being of the floating gate type.

Abstract: The invention relates to a method of and an apparatus for controlling a plurality of mutually communicating actuators, each of the actuators having at least one signal sensor for determining the state of the actuator, with at least one control apparatus generating, in accordance with the state of at least one of the actuators, control signals used for driving controllers of the actuators. In order to avoid overheating of the individual actuators or the control apparatus in case of a large number of actuations by a user, it is provided to determine the temperature of the actuators and the control apparatus cooperating with the actuators and, in case a predetermined temperature threshold value is exceeded in an actuator or the control apparatus, to generate a control signal for non-driving the controllers of the actuators until the excessive temperature detected drops below the temperature threshold value by a defined temperature value.