Abstract: A control signal compensation method is particularly intended for an analog/digital processing system provided with a control loop, including in turn a controller and a monitoring circuit. The method includes storing corrections made by the controller, fast processing such as corrections before transmitting the corrections throughout the control loop, and generating a compensation signal for the latency effects of the controller, by the use of a negative feedback loop provided at the monitoring circuit level.

Abstract: A method is provided for improving the adhesion between a photoresist layer and a dielectric, and an integrated circuit formed according to the same. A conformal dielectric layer is formed over the integrated circuit. An interlevel dielectric layer is formed over the conformal dielectric layer. The interlevel dielectric layer is doped such that the doping concentration allows the layer to reflow while partially inhibiting the adhesion of the doped layer to photoresist at an upper surface of the doped layer. An undoped dielectric layer is formed over the doped dielectric layer. A photoresist layer is formed and patterned over the undoped dielectric layer which adheres to the undoped dielectric layer. The undoped dielectric, the interlevel dielectric and the conformal dielectric layers are etched to form an opening exposing a portion of an underlying conductive region.

Abstract: A planar, capacitive-type, rectangular, and multi-pixel fingerprint sensing array is mounted on the horizontal and generally rectangular top-surface of a dome that extends upward generally from the center of a horizontally disposed and generally rectangular silicon substrate member. The dome is formed by four upward extending and inclined, or tapered, side wall surfaces, at least one wall surface of which carries electrical circuit paths that electrically connected to the various circuit elements of the sensing array. A generally rectangular, encircling and wall-like card carrier assembly includes a generally horizontal upper-surface having a generally centered opening through which only the dome and sensing array project upward. The bottom-surface of the card carrier assembly is mounted to edge portions of the silicon substrate member in a manner to surround and protect all but the upward extending dome.

Abstract: A programming method for a nonvolatile memory includes the steps of: a) determining a current value of the threshold voltage; b) acquiring a target value of the threshold voltage; c) calculating a first number of gate voltage pulses necessary to take the threshold voltage from the current value to the target value; d) applying a second number of consecutive voltage pulses to the gate terminal of the cell, the second number being correlated to the first number and having a uniformly increasing amplitude; e) then measuring a current value of the threshold voltage; and repeating steps c) to e) until a final threshold value is obtained.

Abstract: A static random access memory cell comprising a storage latch having a first upper power supply voltage connection to a first bit line, a second upper power supply voltage connection to a second bit line, and a connection to a lower power supply voltage. A first access circuit connects the storage latch to the first bit line and a second access circuit connects the storage latch to the second bit line, wherein the storage latch is accessed utilizing the first access circuit and the second access circuit.

Abstract: The bond between a flip chip integrated circuit and a substrate is subject to mechanical stress from thermal cycles. This problem is exaggerated when the substrate has a rate of thermal expansion which is appreciably different from that of silicon. This problem is further exaggerated when the IC has a large footprint because it will experience a larger absolute expansion. A solution is proposed to this problem which involves creating an anchoring point. The anchoring point can be in either the IC or the substrate and can be a through-hole or a surface indentation such as a groove or a cutout. The anchoring point is filled with the underfill material during the underfill process. The anchoring point thus provides additional mechanical strength to the bond between the IC and the substrate.

Abstract: An EEPROM is organized in matrix form in word lines and bit lines. Storage cells are placed at the intersections of these lines. The cells include floating gate storage transistors. Groups of cells having separate bit lines but sharing a word line are created. Each group is connected to a group selection transistor. The group selection transistor selectively connects the control gates of the storage transistors to control lines, which provide potentials for enabling programming, erasure or reading of the storage transistors.

Abstract: A semiconductor device structure and method are presented for increasing a breakdown voltage of a junction between a substrate of first conductivity type and a device region. The structure includes a region of second conductivity type in the substrate completely buried in the substrate below and separated from the device region. The region of second conductivity type is located a predetermined distance away from the device region. The distance is sufficient to permit a depletion region to form between the region of second conductivity type and the device region, when a first voltage is applied between the device region and the substrate. The distance also is determined to produce a radius of curvature of the depletion region, when a second voltage that is larger than the first voltage is applied between the device region and the substrate, that is larger than a radius of curvature of the depletion region about the device region that would be formed if the region of second conductivity type were not present.

Abstract: An electronic speed limit notification system comprises a transmitter for transmitting speed limit information ("SLI"), and a receiver for receiving said transmitted SLI, wherein said receiver can be physically located in a vehicle. The SLI comprises one or more speed limits, wherein each speed limit is the maximum or minimum legal speed for specific vehicles on a specific segment of a specific road traveling in a specific direction.

Abstract: A monolithic integrated multiple mode circuit having an output stage, a transfer gate, a control circuit arrangement, and a well contacting region where a well potential may be applied, the multiple mode circuit adapted to be controlled into an output stage mode or an input stage mode by means of control data.

Abstract: A short circuit protection circuit which has a first short circuit protection circuit in parallel with a second short circuit protection circuit is disclosed. The first short circuit protection circuit includes a sense resistor and a comparator for detecting the short circuit, and a transistor and current source for turning off the low side driver when the short circuit is detected. The second short circuit protection circuit includes a current mirror, zener diode, transistor, and current source connected in series. The second short circuit protection circuit is in parallel with the first short circuit protection circuit. The second short circuit protection circuit accelerates the turn-off of the low-side driver with out affecting the stability of the circuit.

Abstract: A non-volatile storage device storing a data bit received from a bitline via an accessing circuit. A coupling circuit couples either the bitline, or a complementary bitline to a biasing circuit dependent on the logic level of the data bit stored in the storage device. The biasing circuit generates a match signal when a data bit having the same logic level as the stored data bit is applied to the bitline.

Abstract: A circuit and method for varying the time of a write cycle. A variable timer circuit is provided coupled to a write simulation circuit. The write simulation circuit receives a signal from a start write sensing circuit indicating that data is being written to memory cells of the array. The write simulation circuit includes a memory cell replicate which replicates the time required for writing data to memory cells of the array. After the memory cell replicate has changed state, a signal is output via a switching circuit to the variable timer circuit for generation of a write termination signal. The memory cells are tested at various write cycle speeds by controlling the variable timer circuit. The variable timer circuit is set to terminate the write as quickly as possible after a successful write to the memory cells has been completed.

Abstract: A layout is provided for an SRAM structure. The layout includes a first storage transistor cross-coupled to a second storage transistor to form an SRAM cell. The source regions of the first and second storage transistors are formed in a common region in the substrate to provide a more compact and dense array. The memory cell also includes a first access transistor and a second access transistor appropriately coupled to the appropriate data storage notes. The gate electrodes for the storage transistors and the access transistors are substantially parallel to each other thus providing advantages in operational characteristics and layout efficiencies. The channel regions are also exactly perpendicular to the gate electrodes and are parallel to each other for each of their respective transistors, thereby obtaining similar benefits. The memory cell is designed having a low aspect ratio, preferably lower than 1.2.

Abstract: A catalytic converter of an engine, such as might be found in an automotive engine system, is capable of being quickly and electrically heated in order to reduce pollution emissions during critical cold start conditions. During cold start conditions, i.e. upon starting the engine, for a predetermined period of time the catalytic converter directly receives electrical power via a quick heating path connecting a catalyst power switch to the catalytic converter. Following the predetermined period of time after which the catalytic converter has been electrically heated, the catalyst power switch is connected to a junction block, such as a starter motor assembly, of the automotive engine system via a normal path.

Abstract: A power down brake latch circuit for dynamically braking a spindle motor in a disk drive system is disclosed. The power down brake latch circuit includes a reservoir capacitor, a smoothing capacitor, a timing circuit, and a logic circuit. The timing circuit includes a voltage divider and a bandgap comparator. The smoothing capacitor absorbs a BEMF voltage from the spindle motor as it rotates after losing power. The timing circuit generates a first signal when a voltage on the smoothing capacitor falls below a threshold. The logic circuit brakes the spindle motor in response to the loss of power and the generation of the first signal.

Abstract: A dynamic access memory (DRAM) device includes a plurality of memory cells for storing data signals. The DRAM device has a row decoding mechanism that allows selected memory cells to be accessed upon receipt of a row address signal during a read operation and a write operation. A latching mechanism is provided and receives and holds onto the data signals from the selected memory cells when activated during the read operation and also isolates itself from the selected memory cells when deactivated during the write operation. An included refresh address generating mechanism generates a plurality of internal row address signals that allows selection of a plurality of memory cells for refreshing the stored data signals. The DRAM device also has a multiplexer mechanism that transmits a plurality of external row address signals to the row decoding mechanism in the write operation.

Abstract: A dynamic random access memory device with reduced refresh duration, and corresponding refresh process includes a plurality of memory cells. All of the memory cells of one and the same column are connected between two column metallizations, and each comprise four insulated-gate field-effect transistors. The four transistors include two storage transistors both possessing the same first quotient of their channel width to their channel length. The four transistors also include two access transistors both possessing the same second quotient of their channel width to their channel length. The ratio of the first quotient to the second quotient is greater than or equal to one. The ratio of the capacitance of a column metallization and the gate/source capacitance of each storage transistor is at least equal to 50. During a specific refresh cycle, several memory cells of one and the same column are selected simultaneously.

Abstract: The additional voltage drop across a guard diode against supply polarity inversion in an integrated bridge circuit for driving an external load and employing two high-side NPN power switches driven by two PNP transistors, all monolithically integrated using a junction-type isolation technique, is substantially eliminated by connecting the emitters of the two PNP drive transistors directly to the positive rail, i.e. to the anode of the guard diode. Integrated PNP transistors are per se intrinsically protected against polarity inversion and when so connected permit to reduce the overall voltage drop across the driving bridge circuit. Using a Zener diode as the guard diode and a second Zener diode connected in opposition to the first Zener between the cathode thereof and the negative supply rail an additional spike protection of the circuit's components is implemented.

Abstract: A control and monitoring circuit for a power switch comprises a first portion (20) connected to this switch and fed with reference to a floating voltage (V.sub.F) of an electrode of this switch, a second portion (10) connected to circuits external to the switch and fed with reference to a fixed voltage, a coder (40) arranged on the side of the second portion and a suitable decoder (50) arranged on the side of the first portion.