Patents Assigned to STMicroelectronics
  • Patent number: 8836143
    Abstract: A chip package includes a substrate, an integrated circuit proximate a top surface of the substrate, and a cap comprising encapsulant that encapsulates the integrated circuit on at least a portion of the top surface of the substrate. The chip package further includes at least one extension feature positioned on at least a portion of the top surface of the substrate. The at least one extension feature also comprises the encapsulant and extends from the cap to a perimeter of the substrate.
    Type: Grant
    Filed: September 6, 2012
    Date of Patent: September 16, 2014
    Assignee: STMicroelectronics Asia Pacific Pte Ltd.
    Inventor: Jing-en Luan
  • Patent number: 8836111
    Abstract: Described herein is a semiconductor integrated device assembly, which envisages: a package defining an internal space; a first die including semiconductor material; and a second die, distinct from the first die, also including semiconductor material; the first die and the second die are coupled to an inner surface of the package facing the internal space. The second die is shaped so as to partially overlap the first die, above the inner surface, with a portion suspended in cantilever fashion above the first die, by an overlapping distance.
    Type: Grant
    Filed: June 12, 2013
    Date of Patent: September 16, 2014
    Assignees: STMicroelectronics S.r.l., STMicroelectronics International N.V.
    Inventors: Sebastiano Conti, Benedetto Vigna
  • Patent number: 8838953
    Abstract: A provisioning device is provided that communicates over a trusted out-of-band communications channel to digital electronic devices in order to exchange security data such as passwords and private or public keys, thereby establishing a secure communications network between the devices.
    Type: Grant
    Filed: June 5, 2008
    Date of Patent: September 16, 2014
    Assignee: STMicroelectronics, Inc.
    Inventor: Oleg Logvinov
  • Patent number: 8835923
    Abstract: The semiconductor wafer for a silicon-on-insulator integrated circuit comprises an insulating region located between a first semiconductor substrate intended to receive the integrated circuit and a second semiconductor substrate containing at least one buried layer comprising at least one metal silicide.
    Type: Grant
    Filed: September 14, 2012
    Date of Patent: September 16, 2014
    Assignee: STMicroelectronics (Rousset) SAS
    Inventor: Pascal Fornara
  • Patent number: 8837153
    Abstract: An insulating body embeds at least one integrated circuit chip and a first and second exposed heat sink exposed on a free surface opposite a mounting surface of the body. An external heat-sink extends above the free surface. The external heat-sink includes a first dissipative portion and a second dissipative portion for contacting the first and second heat-sinks on the free surface, respectively, as well as an insulating portion for electrically insulating the first dissipative portion from the second dissipative portion. The first dissipative portion and the second dissipative portion are symmetrical with respect to the insulating portion. An extension of the external heat-sink may provide a stabilizing element. The extension of the external heat-sink may alternatively thermally and electrically interconnect two insulating bodies, each body embedding at least one integrated circuit chip.
    Type: Grant
    Filed: June 27, 2012
    Date of Patent: September 16, 2014
    Assignee: STMicroelectronics S.r.l.
    Inventor: Cristiano Gianluca Stella
  • Publication number: 20140253213
    Abstract: An amplifier has a first pull-up path coupled between a voltage supply node and an output node, and a pull-down path coupled between the output node and a ground supply node. A second pull-up path is coupled between the voltage supply node and the output node. The second pull-up path is actuated by a feedback signal and biased by a biasing signal. An inverter circuit is operable to invert the signal at the amplifier output node to generate the feedback signal. A biasing circuit is configured to generate the biasing signal. The biasing circuit is configured to control a relative strength of the pull-down path to the second pull-up path, wherein the pull-down path is stronger than the second pull-up path in a manner that is consistently present over all PVT corners.
    Type: Application
    Filed: May 19, 2014
    Publication date: September 11, 2014
    Applicant: STMICROELECTRONICS INTERNATIONAL N.V.
    Inventors: Adeel Ahmad, Chandrajit Debnath
  • Publication number: 20140251805
    Abstract: The present disclosure relates to a sensor for detecting hydrogen ions in an aqueous solution comprising a support, a reference electrode, a working electrode and a counter electrode supported by said support, the reference electrode being made of a material comprising silver and silver chloride, the counter electrode being made of a conductive material. The working electrode comprises a substrate and a layer made of an inherently electrically conductive polymer of the polythiophene or polyaniline (PANI) or polypyrrole class.
    Type: Application
    Filed: March 7, 2014
    Publication date: September 11, 2014
    Applicant: STMicroelectronics S.r.l.
    Inventors: Giovanna Salzillo, Rossana Scaldaferri, Valeria Casuscelli, Luigi Giuseppe Occhipinti
  • Publication number: 20140252507
    Abstract: Embodiments of the present disclosure are related to MEMS devices having a suspended membrane that are secured to and spaced apart from a substrate with a sealed cavity therebetween. The membrane includes openings with sidewalls that are closed by a dielectric material. In various embodiments, the cavity between the membrane and the substrate is formed by removing a sacrificial layer through the openings. In one or more embodiments, the openings in the membrane are closed by depositing the dielectric material on the sidewalls of the openings and the upper surface of the membrane.
    Type: Application
    Filed: March 5, 2013
    Publication date: September 11, 2014
    Applicant: STMICROELECTRONICS PTE LTD.
    Inventors: Ravi Shankar, Olivier Le Neel, Shian Yeu Kam, Tien Choy Loh
  • Publication number: 20140252524
    Abstract: An embodiment of array of Geiger-mode avalanche photodiodes, wherein each photodiode is formed by a body of semiconductor material, having a first conductivity type and housing an anode region, of a second conductivity type, facing a top surface of the body, a cathode-contact region, having the first conductivity type and a higher doping level than the body, facing a bottom surface of the body, an insulation region extending through the body and insulating an active area from the rest of the body, the active area housing the anode region and the cathode-contact region. The insulation region is formed by a first mirror region of polycrystalline silicon, a second mirror region of metal material, and a channel-stopper region of dielectric material, surrounding the first and second mirror regions.
    Type: Application
    Filed: May 19, 2014
    Publication date: September 11, 2014
    Applicant: STMICROELECTRONICS S.r.l.
    Inventors: Delfo Nunziato SANFILIPPO, Piero Giorgio FALLICA
  • Publication number: 20140254292
    Abstract: Described herein are various principles for designing, manufacturing, and operating integrated circuits having functional components and one or more metal interconnect layers, where the dimensions of signal lines of the metal interconnect layers are larger than dimensions of the functional components. In some embodiments, a signal line may have a width greater than a width of a terminal of a functional component to which the signal line is connected. In some embodiments, two functional components formed in a same functional layer of the integrated circuit may be connected to metal signal lines in different metal interconnect layers. Further, the metal signal lines of the different metal interconnect layers may overlap some distance.
    Type: Application
    Filed: May 27, 2014
    Publication date: September 11, 2014
    Applicant: STMicroelectronics, Inc.
    Inventor: David V. Carlson
  • Publication number: 20140252509
    Abstract: A micromechanical structure of a MEMS device, integrated in a die of semiconductor material provided with a substrate and having at least a first axis of symmetry lying in a horizontal plane, has a stator structure, which is fixed with respect to the substrate, and a rotor structure, having a suspended mass, mobile with respect to the substrate and to the stator structure as a result of an external action, the stator structure having fixed sensing electrodes capacitively coupled to the rotor structure; a compensation structure is integrated in the die for compensation of thermo-mechanical strains. The compensation structure has stator compensation electrodes, which are fixed with respect to the substrate, are capacitively coupled to the rotor structure, and are arranged symmetrically to the fixed sensing electrodes with respect to the first axis of symmetry.
    Type: Application
    Filed: February 25, 2014
    Publication date: September 11, 2014
    Applicant: STMicroelectronics S.r.l.
    Inventor: Angelo Antonio Merassi
  • Patent number: 8829622
    Abstract: An integrated circuit including at least one isolating trench that delimits an active area made of a monocrystalline semiconductor material, the or each trench comprising an upper portion including an insulating layer that encapsulates a lower portion of the trench, the lower portion being at least partly buried in the active area and the encapsulation layer comprising nitrogen or carbon.
    Type: Grant
    Filed: June 13, 2012
    Date of Patent: September 9, 2014
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventors: Grégory Bidal, Laurent Favennec, Raul Andres Bianchi
  • Patent number: 8829670
    Abstract: The present disclosure is directed to a device that includes a first substrate having a first plurality of hollow pillars on the first substrate and a first plurality of channels in the first substrate coupled to the first plurality of hollow pillars. The device includes a second substrate attached to the first substrate, the second substrate having a second plurality of hollow pillars on the second substrate and a second plurality of channels in the second substrate coupled to the second plurality of hollow pillars, the first plurality of hollow pillars being coupled to the second plurality of hollow pillars to allow a fluid medium to move through the substrate to cool the first substrate and the second substrate.
    Type: Grant
    Filed: June 28, 2013
    Date of Patent: September 9, 2014
    Assignees: STMicroelectronics, Inc., International Business Machines Corporation
    Inventors: John H. Zhang, Lawrence A. Clevenger, Carl Radens, Yiheng Xu, Edem Wornyo
  • Patent number: 8829950
    Abstract: A Local Interconnect Network (LIN) driver circuit employs a charging/discharging current applied to the gate of a driver transistor coupled to an LIN bus. The charging current includes a constant charging current and an additional soft charging current, whereas the discharging current includes a constant discharging current and an additional soft discharging current. As a result of the soft charge/discharge components, there is a significant reduction in electromagnetic emission on the LIN bus.
    Type: Grant
    Filed: December 13, 2012
    Date of Patent: September 9, 2014
    Assignee: STMicroelectronics R&D (Shanghai) Co. Ltd
    Inventors: Tina Shen, Anderson Yin
  • Patent number: 8831160
    Abstract: An apparatus includes a first clock source, a second clock source and circuitry configured to supply a clock signal to a circuit. The circuitry operates to change the clock signal from one frequency to another different frequency. This change is made in a manner whereby no clock signal is supplied during a period of time when the change from the one frequency to the another different clock frequency is being made.
    Type: Grant
    Filed: January 17, 2013
    Date of Patent: September 9, 2014
    Assignees: STMicroelectronics (Research & Development) Limited, STMicroelectronics (Grenoble 2) SAS
    Inventors: Andrew Ferris, Ignazio Antonino Urzi
  • Patent number: 8828797
    Abstract: A three-dimensional integrated structure is fabricated by assembling at least two parts together, wherein each part contains at least one metallic line covered with a covering region and having a free side. A cavity is formed in the covering region of each part, that cavity opening onto the metallic line. The two parts are joined together with the free sides facing each other and the cavities in each covering region aligned with each other. The metallic lines are then electrically joined to each other through an electromigration of the metal within at least one of the metallic lines, the electromigrated material filling the aligned cavities.
    Type: Grant
    Filed: August 31, 2011
    Date of Patent: September 9, 2014
    Assignee: STMicroelectronics SA
    Inventors: Perceval Coudrain, Yacine Felk, Patrick Lamontagne
  • Patent number: 8829837
    Abstract: A driving apparatus for an electromagnetic load, said apparatus having at least one pair of first and second transistors arranged so as to form a current path with the electromagnetic load for discharging the current produced by the electromagnetic load. The first transistor has an inherent diode between the non-drivable terminals and the apparatus is configured to control switching of the pair of first and second transistors, to diode-connect the second transistor, with said first and second transistors switched off, so that the current produced by said electromagnetic load, crossing said inherent diode, creates an overvoltage between the terminals of the second diode-configured transistor such to exceed the conduction threshold voltage thereof.
    Type: Grant
    Filed: September 29, 2010
    Date of Patent: September 9, 2014
    Assignee: STMicroelectronics S.r.l.
    Inventor: Ezio Galbiati
  • Patent number: 8830685
    Abstract: A flexible sheet of organic polymer material, may include a monolithically fabricated array of one or more types of cells juxtaposed among them to form a multi-cell sheet. Each cell may include a self consistent, organic base integrated circuit, replicated in each cell of same type of the array, and shares, in common with other cells of same type, at least a conductor layer of either an electrical supply rail of the integrated circuit or of an input/output of the integrated circuit. A piece of the multi-cell, sheet including any number of self consistent integrated circuit cells, may be severed from the multi-cell sheet by cutting the sheet along intercell boundaries or straight lines, with a reduced affect on the operability of any cell spared by the cutting.
    Type: Grant
    Filed: February 25, 2011
    Date of Patent: September 9, 2014
    Assignee: STMicroelectronics S.R.L.
    Inventor: Manuela La Rosa
  • Patent number: 8830098
    Abstract: The invention concerns a sigma-delta switched capacitor analog to digital converter (ADC) having: an input line for receiving a signal to be converted; first, second and third inputs for respectively receiving first, second and third test voltages; and switching circuitry adapted to apply, during a test mode of the sigma-delta ADC, a ternary test signal to the input line by periodically selecting, based on a digital test control signal, one of the first, second or third test voltages to be applied to the input line.
    Type: Grant
    Filed: June 28, 2011
    Date of Patent: September 9, 2014
    Assignee: STMicroelectronics International NV
    Inventors: Salvador Mir, Haralampos Stratigopoulos, Matthieu Dubois
  • Patent number: 8829943
    Abstract: An analog disconnection envelope detection circuit having a low power supply detects a high speed, high differential voltage disconnect state on a data line. Level-shifting circuitry shifts the voltage level of two input signals by the value of a detection threshold voltage, generates differential signals used to indicate conditions of the input signals, and mitigates effects of input differential signal common-mode voltage on the detection operation. Circuitry is provided to equalize VDS of detecting tail current sources, thereby eliminating errors resulting from VDS mismatch of tail current sources. Comparator circuitry compares the sets of differential signals and indicates when the absolute difference between the two input signals is greater than a reference voltage. Output circuitry generates a disconnect signal corresponding to the disconnect condition.
    Type: Grant
    Filed: October 19, 2012
    Date of Patent: September 9, 2014
    Assignee: STMicroelectronics International N.V.
    Inventor: Daljeet Kumar