Abstract: An image sensor includes an array of pixels. Each pixel has at least one photo-sensitive element. Readout circuitry receives an analog signal from each pixel at a first time and at a second time, between which the analog signal changes. The image sensor further includes associated support circuitry which is a source of time variant noise. The signal level at both first and second times includes pixel noise. Sample and hold circuitry is provided to maintain substantially level at least a proportion of this support circuitry noise time invariant at the sensor output between the first time and the second time.

Abstract: A method of distributing media content over networks where content is shared includes coupling downloading metadata, which is accessed to start downloading media contents from the network, with semantic metadata representative of the semantic information associated with at least one of the content, and with source metadata indicative of the source of the media content. At least one of the semantic and the source metadata may be made accessible without downloading, even partially, the media content. A digital signature may also be applied to the metadata to enable the verification that, at reception, the metadata is intact and has not been subjected to malicious tampering.

Abstract: A method is for decoding a pulse signal modulated through a transmitted reference modulation scheme. The modulated pulse signal may include, repetitively, a reference pulse followed by an information pulse delayed with a delay. The method may include subtracting or adding from the modulated pulse signal, a version of the modulated pulse signal delayed with the delay for obtaining a processed signal, and performing a non-coherent detection on the processed signal.

Abstract: The device may include a contactless element and a set of least two auxiliary elements. Each auxiliary element may include a slave SWP interface connected to a same master SWP interface of the contactless element through a SWP link, and a management module configured for activating at once only one slave SWP interface on the SWP link.

Abstract: A main blind hole is formed in a front face of a wafer having a rear face. A through capacitor is formed in the main blind hole including a conductive outer electrode, a dielectric intermediate layer, and a filling conductive material forming an inner electrode. Cylindrical portions of the outer electrode, the dielectric intermediate layer and the inner electrode have front ends situated in a plane of the front face of the wafer. A secondary rear hole is formed in the rear face of the wafer to reveal a bottom of the outer electrode. A rear electrical connection is made to contact the bottom of the outer electrode through the secondary rear hole. A through hole via filled with a conductive material is provided adjacent the through capacitor. An electrical connection is made on the rear face between the rear electrical connection and the through hole via.

Abstract: A dielectric wafer has, on top of its front face, a front electrical connection including an electrical connection portion. A blind hole passes through from a rear face of the wafer to at least partially reveal a rear face of the electrical connection portion. A through capacitor is formed in the blind hole. The capacitor includes a first conductive layer covering the lateral wall and the electrical connection portion (forming an outer electrode), a dielectric intermediate layer covering the first conductive layer (forming a dielectric membrane), and a second conductive layer covering the dielectric intermediate layer (forming an inner electrode). A rear electrical connection is made to the inner electrode.

Abstract: A memory bank includes memory cells and an additional cell to determine an operating voltage of the memory bank. The additional cell has an operating margin that is less than a corresponding operating margin of the other memory cells in the memory bank.

Abstract: An anticollision method for an NFC device wherein, in reader mode, a variation of a piece of information representative of the amplitude of the signal in an antenna of the device is monitored, and if this piece of information exceeds a threshold, the device is switched to the card mode.

Abstract: In managing incoming bus traffic storage for store cell memory (SCM) in a sequential-write, random-read system, a priority encoder system can be used to find a next empty cell in the sequential-write step. Each cell in the SCM has a bit that indicates whether the cell is full or empty. The priority encoder encodes the next empty cell using these bits and the current write pointer. The priority encoder can also find next group of empty cells by being coupled to AND operators that are coupled to each group of cells. Further, a cell locator selector selects a next empty cell location among priority encoders for cell groups of various sizes according to an opcode by appending ‘0’s to cell locations outputs from priority encoders that are smaller than the size of the SCM.

Abstract: A microelectromechanical device includes: a body; a movable mass, elastically coupled to the body and oscillatable with respect to the body according to a degree of freedom; a frequency detector, configured to detect a current oscillation frequency of the movable mass; and a forcing stage, capacitively coupled to the movable mass and configured to provide energy to the movable mass through forcing signals having a forcing frequency equal to the current oscillation frequency detected by the frequency detector, at least in a first transient operating condition.

Abstract: Generating by a digital processing device, of a first digital image from a second digital image, by: for each pixel of the second image, determining a pixel luminance; dividing the interval ranging from the lowest to the highest luminance into a plurality of sub-intervals; and determining the value of at least one pixel of the first image by multiplying the value of a pixel of the second image by a gain determined by interpolation by taking into account the distance of the pixel luminance of the second image to the limits of the sub-interval containing this luminance.

Abstract: The gate of a drive transistor having a drain and source is discharged by a circuit including a sensing circuit configured to sense a drain-to-source voltage of the drive transistor. A first current sink path is coupled to the gate of the drive transistor. The first current sink path applies a high discharge current to the gate of the drive transistor when the sensing current senses a lower drain-to-source voltage of the drive transistor. A second current sink path is also coupled to the gate of the drive transistor. The second current sink path is configured to apply a low discharge current to the gate of the drive transistor when the sensing current senses a higher drain-to-source voltage of the drive transistor.

Abstract: A method for manufacturing solder bumps for through vias in a substrate having a first surface and a second surface opposed to each other. The method includes the steps of forming a blind hole extending in the substrate from the first surface for each via and filling each blind hole with a conductive filler; a deepest part of each filler includes a bump portion made of a solder material. The method further includes the step of removing a part of the substrate extending from the second surface to have at least the bump portions protrude from the substrate. The non-protruding part of each filler defines the corresponding via and the bump portion defines the corresponding bump.

Abstract: An integrated MEMS structure includes a driving assembly anchored to a substrate and actuated with a driving movement. A pair of sensing masses suspended above the substrate and coupled to the driving assembly via elastic elements is fixed in the driving movement and performs a movement along a first direction of detection, in response to an external stress. A coupling assembly couples the pair of sensing masses mechanically to couple the vibration modes. The coupling assembly is formed by a rigid element, which connects the sensing masses and has a point of constraint in an intermediate position between the sensing masses, and elastic coupling elements for coupling the rigid element to the sensing masses to present a first stiffness to a movement in phase-opposition and a second stiffness, greater than the first, to a movement in phase, of the sensing masses along the direction of detection.

Abstract: Silicon germanium regions are formed adjacent gates electrodes over both n-type and p-type regions in an integrated circuit. A hard mask patterned by lithography then protects structures over the p-type region while the silicon germanium is selectively removed from over the n-type region, even under remnants of the hard mask on sidewall spacers on the gate electrode. Silicon germanium carbon is epitaxially grown adjacent the gate electrode in place of the removed silicon germanium, and source/drain extension implants are performed prior to removal of the remaining hard mask over the p-type region structures.

Abstract: A method distributes personalized circuits to one or more parties. The method distributes a generic circuit to each party, encrypts a unique personalization value using a secret encryption key, and transmits each encrypted personalization value to the corresponding party. Each party then stores the encrypted personalization value in their circuit. The stored encrypted personalization value allows a piece of software to be properly executed by the circuit. A semiconductor integrated circuit is arranged to execute a piece of software that inputs a personalization value as an input parameter. The circuit comprises a personalization memory arranged to store an encrypted personalization value; a key memory for storing a decryption key; a control unit comprising a cryptographic circuit arranged to decrypt the encrypted personalization value using the decryption key; and a processor arranged to receive the decrypted personalization value and execute the software using the decrypted personalization value.

Abstract: An electronic device may include a bottom interconnect layer and an integrated circuit (IC) carried by the bottom interconnect layer. The electronic device may further include an encapsulation material on the bottom interconnect layer and laterally surrounding the IC. The electronic device may further include electrically conductive pillars on the bottom interconnect layer extending through the encapsulation material. At least one electrically conductive pillar and adjacent portions of encapsulation material may have a reduced height with respect to adjacent portions of the IC and the encapsulation material and may define at least one contact recess. The at least one contact recess may be spaced inwardly from a periphery of the encapsulation material.

Abstract: A memory device includes first and second inverters cross-coupled between first and second nodes. The first inverter is configured to be supplied by a first supply voltage via a first transistor and the second inverter is configured to be supplied by the first supply voltage via a second transistor. A first control circuit is configured to control a gate node of the first transistor based on the voltage at the second node and at a gate node of the second transistor. A second control circuit is configured to control the gate node of the second transistor based on the voltage at the first node and at the gate node of the first transistor.

Abstract: A MEMS transducer has a micromechanical sensing structure and a package. The package is provided with a substrate, carrying first electrical-connection elements, and with a lid, coupled to the substrate to define an internal cavity, in which the micromechanical sensing structure is housed. The lid is formed by: a cap layer having a first surface and a second surface, set opposite to one another, the first surface defining an external face of the package and the second surface facing the substrate inside the package; and a wall structure, set between the cap layer and the substrate, and having a coupling face coupled to the substrate. At least a first electrical component is coupled to the second surface of the cap layer, inside the package, and the coupling face of the wall structure carries second electrical-connection elements, electrically connected to the first electrical component and to the first electrical-connection elements.

Abstract: An insulating body incorporates at least one integrated circuit chip and includes a mounting surface for mounting to a board and a free surface opposite the mounting surface. A heatsink is attached to the insulating body at the free surface. The heatsink includes at least one stabilizing element. The stabilizing element includes an attachment portion extending at least partially transversely to the free surface beyond a peripheral boundary of the free surface when considered in plan view. The attachment portion has a binding end bound to the free surface and a free end opposite the binding end. The stabilizing element also has a mounting portion extending from the free end of the attachment portion at least up to a plane of the mounting surface.