Abstract: A Schottky photodiode may include a monocrystalline semiconductor substrate having a front surface, a rear surface, and a first dopant concentration and configured to define a cathode of the Schottky photodiode, a doped epitaxial layer over the front surface of the monocrystalline semiconductor substrate having a second dopant concentration less than the first dopant concentration, and parallel spaced apart trenches in the doped epitaxial layer and having of a depth less than a depth of the doped epitaxial layer.

Abstract: A memory architecture includes a plurality of local input and output circuitries, with each local input and output circuitry associated with at least one memory bank. The memory architecture also includes a global input and output circuitry, which includes a plurality of global sub-write circuitries, is coupled to the plurality of local input and output circuitries One global sub-write circuitry is enabled and provides a write-data to a selected local input and output circuitry.

Abstract: A thin film capacitor is characterized by forming a lower electrode, coating a composition onto the lower electrode without applying an annealing process having a temperature of greater than 300° C., drying at a predetermined temperature within a range from ambient temperature to 500° C., and calcining at a predetermined temperature within a range of 500 to 800° C. and higher than a drying temperature. The process from coating to calcining is performed the process from coating to calcining once or at least twice, or the process from coating to drying is performed at least twice, and then calcining is performed once. The thickness of the dielectric thin film formed after the first calcining is 20 to 600 nm. The ratio of the thickness of the lower electrode and the thickness of the dielectric thin film formed after the initial calcining step (thickness of lower electrode/thickness of the dielectric thin film) is preferably in the range 0.10 to 15.0.

Abstract: A voltage controlled variable resistor circuit is configured to variably attenuate a variable source signal. A fixed attenuation circuit is coupled to receive the variable source signal and output an attenuated variable source signal. The variable source signal is further applied across a variable resistive divider formed of a fixed resistive circuit and a variable resistive circuit. The variable resistive circuit has a first input configured to receive the attenuated variable source signal and a second input configured to receive a variable resistance control signal. The variable resistive circuit is configured to have a resistance which is variable in response to the attenuated variable source signal and the variable resistance control signal.

Abstract: A method for bonding a first copper element onto a second copper element including forming a crystalline copper layer enriched in oxygen on each of surfaces of each of the first and second elements through which the elements will be in contact, the total thickness of both layers being less than 6 nm, which includes: a) polishing the surfaces so as to obtain a roughness of less than 1 nm RMS, and hydrophilic surfaces, b) cleaning the surfaces to suppress presence of particles due to the polishing and the major portion of corrosion inhibitors, and c) putting both crystalline copper layer enriched in oxygen in contact with each other.

Abstract: A switch for an analog signal may include a main MOS transistor whose source forms an input terminal of the switch and whose drain forms an output terminal of the switch, a capacitor having a first terminal permanently connected to the source of the main transistor, a circuit for charging the capacitor, and a first auxiliary transistor configured to connect the second terminal of the capacitor to the gate of the main transistor in response to a control signal. The charge circuit may include a resistor permanently connecting the second terminal of the capacitor to a power supply line. The capacitor and the resistor may form a high-pass filter having a cutoff frequency lower than the frequency of the analog signal.

Abstract: A by-pass circuit includes a first power MOS with an intrinsic diode, a first conduction terminal coupled to a cathode, a second conduction terminal coupled to an anode, and a control terminal. A tank capacitor is coupled to the anode. A second MOS has a first and second conduction terminals, a control terminal, and a turn-on threshold smaller than that of the intrinsic diode, the first conduction terminal thereof coupled to the cathode and the control terminal coupled to the anode, so the first MOS turns on when the array of cells are sub-illuminated. An oscillator and charge pump are supplied through the second conduction terminal of the second MOS to charge the tank capacitor. A control circuit is coupled to the control terminal of the first power MOS to switch it based upon a voltage of the tank capacitor and sign of the voltage between the cathode and anode.

Abstract: A surface mount chip including, on the side of a surface, first and second pads of connection to an external device, wherein, in top view, the first pad has an elongated general shape, and the second pad is a point-shaped pad which is not aligned with the first pad.

Abstract: A MEMS acoustic transducer, for example, a microphone, includes a substrate provided with a cavity, a supporting structure, fixed to the substrate, a membrane having a perimetral edge and a centroid, suspended above the cavity and fixed to the substrate the membrane configured to oscillate via the supporting structure. The supporting structure includes a plurality of anchorage elements fixed to the membrane, and each anchorage element is coupled to a respective portion of the membrane between the centroid and the perimetral edge of the membrane.

Abstract: A device for protecting an integrated circuit against overvoltages, the device being formed inside and on top of a semiconductor substrate of a first conductivity type and including: a capacitor including a well of the second conductivity type penetrating into the substrate and trenches with insulated walls formed in the well and filled with a conductive material; and a zener diode formed by the junction between the substrate and the well.

Abstract: A method for writing and reading data memory cells, comprising: defining in a first memory zone erasable data pages and programmable data blocks; and, in response to write commands of data, writing data in erased blocks of the first memory zone, and writing, in a second memory zone, metadata structures associated with data pages and comprising, for each data page, a wear counter containing a value representative of the number of times that the page has been erased.

Abstract: A multilevel interconnect structure for a semiconductor device includes an intermetal dielectric layer with funnel-shaped connecting vias. The funnel-shaped connecting vias are provided in connection with systems exhibiting submicron spacings. The architecture of the multilevel interconnect structure provides a low resistance connecting via.

Abstract: A capacitive sensing structure is formed from first electrically conductive sensor structures electrically coupled to each other in a first direction, and second electrically conductive sensor structures electrically coupled to each other in a second direction. Each first electrically conductive sensor structure includes a first diamond-shaped central region with electrically coupled first finger structures extending away therefrom. Each second electrically conductive sensor structure includes a second diamond-shaped central region with electrically conducting second finger structures extending away therefrom. Each second finger structure extends between two adjacent ones of the first finger structures. Floating structures may be included within an opening formed in the first diamond shaped central region. Floating structures may further be included between the first and second finger structures.

Abstract: A method for demodulating phase quadrature modulated signals in a band of channels includes transposing the band around zero, and selecting a channel in the transposed band. A first pair of phase quadrature signals forming a first complex signal is extracted from the selected channel. A second pair of phase quadrature signals forming a second complex signal is extracted from a symmetrical channel of the selected channel. The method further includes establishing a correlation product based on the first and second complex signals, and correcting the two complex signals to make the correlation product tend towards zero.

Abstract: A touch screen having a capacitive touch-sensitive pad overlaying a display area incorporates one or more slide features each having conductive plates. The conductive plates are located outside the display area of the touch screen and are powered via one or more connections to existing touch sensor circuitry comprising the touch-sensitive pad. The slide features of the touch screen do not obstruct a user's view of the display screen and, when compared to conventional touch screen slide features, reduce the circuitry required for detecting and/or processing a slide touch.

Abstract: An embodiment of a 4D data ultrasound imaging system includes a matrix of transducer elements suitable for transmitting and for receiving ultrasound signals, said transducer elements being divided into sub-matrixes suitable for receiving in a delayed way a same acoustic signal, a plurality of reception channels with one of said reception channels being associated with one of said transducer elements, a beamformer device including a plurality of storage cells arranged in re-phasing matrixes, each re-phasing matrix being associated with a corresponding sub-matrix with each row associated with one of said transducer elements, said storage cells including an input storage stage that is selectively associated with a row and a reading output stage that is selectively associated with a buffer; each storage cell that belongs to a same column has the input stage that is dynamically activated in sequential times with respect to another storage cell of the same column for storing the same delayed acoustic signal, said s

Abstract: Described herein is a preamplifier circuit for a capacitive acoustic transducer provided with a MEMS detection structure that generates a capacitive variation as a function of an acoustic signal to be detected, starting from a capacitance at rest; the preamplifier circuit is provided with an amplification stage that generates a differential output signal correlated to the capacitive variation. In particular, the amplification stage is an input stage of the preamplifier circuit and has a fully differential amplifier having a first differential input (INP) directly connected to the MEMS detection structure and a second differential input (INN) connected to a reference capacitive element, which has a value of capacitance equal to the capacitance at rest of the MEMS detection structure and fixed with respect to the acoustic signal to be detected; the fully differential amplifier amplifies the capacitive variation and generates the differential output signal.

Abstract: Adaptive scaling digital techniques attempt to place the system close to the timing failure so as to maximize energy efficiency. Rapid recovery from potential failures is usually by slowing the system clock and/or providing razor solutions (instruction replay.) These techniques compromise the throughput. This application presents a technique to provide local in-situ fault resilience based on dynamic slack borrowing. This technique is non-intrusive (needs no architecture modification) and has minimal impact on throughput.

Abstract: A method is provided for controlling a converter of the multiphase interleaving type. According to the method, there is detected when a change of the load applied to an output terminal of the converter occurs. All the phases of the converter are simultaneously turned off, and a driving interleaving phase shift is recovered so as to restart a normal operation of the converter. A controller for carrying out such a method is also provided.

Abstract: An embodiment of a non-volatile memory device includes: a memory array, having a plurality of non-volatile logic memory cells arranged in at least one logic row, the logic row including a first row and a second row sharing a common control line; and a plurality of bit lines. Each logic memory cell has a direct memory cell, for storing a logic value, and a complementary memory cell, for storing a second logic value, which is complementary to the first logic value in the corresponding direct memory cell. The direct memory cell and the complementary memory cell of each logic memory cell are coupled to respective separate bit lines and are placed one in the first row and the other in the second row of the respective logic row.