Abstract: A software conversion tool that facilitates automated conversion of a software program from one operating environment to another. More particularly, a computer program is compiled using a compiler for a software environment other than a software environment assumed by the computer program. As a result, the compiler produces an error message, and, in response to the error message, source code within the computer program is automatically modified in order to remove a condition causing the error. The software conversion tool acts in concert with the compiler, which may be a standard compiler, to form in effect an error-correcting compiler, i.e., a compiler that instead of only detecting errors and presenting them to the user, is able to actually correct errors such that they do not occur during recompilation.

Abstract: A method and apparatus for dynamically switching the relative priorities of the load buffer and store buffer with respect to external memory resources in a superscalar processor. According to a first embodiment, a protocol dictates that the load buffer always prevails until the store buffer reaches a certain "high water mark," (an upper threshold) at which time the store buffer gains priority. After the store buffer has gained priority, it continues to access the memory until it is depleted to a "low water mark," (a lower threshold) at which time the load buffer regains priority. Whenever the store buffer reaches the high water mark, it gains priority until it drains down to the low water mark. This reduces the tendency for the store buffer to become full and block the processor. According to a second embodiment, the load buffer prevails if it is above its high water mark.

Abstract: A CMOS integrated circuit regulator for mixed mode integrated circuits reduces digital switching noise through use of a clamped dual source follower circuit and a charge reservoir bypass capacitor. Relatively constant current is provided to the CMOS logic during transitions to minimize switching noise.

Abstract: A method and apparatus that allows a Web page designer to specify that an audio file linked to a Web page should be prefetched before user input is accepted. Web browser software prefetches the audio file if there is enough room in a temporary memory to store the file. The invention also allows a Web page designer to specify the text over which the user must place the cursor to play the audio file. When the temporary memory is full and an audio file needs to be prefetched, the browser deletes files from the temporary memory until there is enough room in the temporary memory for the prefetched audio file. Files are deleted in a least-recently-referenced, first-out order.

Abstract: A microprocessor in a computer system processes an instruction stream comprising instructions of a plurality of instruction types including an information retrieval instruction type. The microprocessor comprises a register set, a pending fault flag set, a functional unit, an information retrieval subsystem, and a control subsystem. The register set comprises a plurality of registers, each register for storing information. The pending fault flag set comprises a plurality of pending fault flags each associated with one of said registers, each pending fault flag having selected conditions including a pending fault condition and a no pending fault condition. The functional unit performs processing operations in response to information input thereto. The information retrieval subsystem initiates an information retrieval operation to retrieve of information from said information storage subsystem for storage in a register.

Abstract: A system and method for displaying still video images related to video content in an interactive broadcast television system. The system and method of the present invention may also be used for simulating an Internet home page on an interactive television system. The present invention thus supports hyperlinked web-like navigational capabilities in an interactive television system. According to the method of the present invention, the video delivery system provides or broadcasts one or more audio/video channels each comprising video content and also provides or broadcasts at least one still image channel comprising a plurality of still video images, preferably MPEG-2 compressed still images. The user or viewer can select options displayed on the television screen to view desired information.

Abstract: Apparatus, methods, systems and computer program products are disclosed that optimize a programmed loop that stores pointer variables in an array in a card-marked heap. These methods also optimize garbage collection operations on these pointer variables. Instead of implementing a write-barrier in the body of a programmed loop, the loop is parameterized. This parameterization is associated with the pointer array stored in the heap. This parameterization specifies the first and last modified elements in the array. It further specifies the stride (which indicates how many elements are skipped to reach the next modified element of the array). The parameterization is modified by successive loops that access the array. During a garbage collection operation, the array's parameterization is used to optimize the process of locating modified elements in the array.

Abstract: An inductive compensation apparatus for smooth compensation of a transmission bus and methods of operating the same result in improved impedance of the transmission bus for transfer of data signals. The inductive compensation apparatus having an input and an output and a transmission bus with an effective impedance comprises a first capacitance connected to the input and a second capacitance connected to the output. A first bus compensator is connected between the input and the first capacitance to compensate the first capacitance and raise the impedance of the transmission bus. A second bus compensator is connected between the first capacitance and the second capacitance to compensate the first capacitance and the second capacitance and raise the impedance of the transmission bus. A third bus compensator is connected between the second capacitance and the output to compensate the second capacitance and raise the impedance of the transmission bus for improved data transfers on the transmission bus.

Abstract: A vector processor with a vector mask control unit provides an efficient approach for execution of conditional loops by a vector processor. The vector mask control unit includes respective vector masks for source and destination vector registers to specify the vector elements that should participate in the execution operation. Only the vector elements that correspond to active mask elements then participate in the execution operation, thus increasing the efficiency of the vector processor in executing conditional loops. Providing a vector mask control unit also allows the vector processor to perform a variety of functions more efficiently.

Abstract: An extended binary encoding for a plurality of inputs is sensed using a two-phase process. In a first phase binary values are sensed at the inputs. In the second phase, inputs sensed as having a first binary signal value are driven to a second binary value to test whether other inputs which had the first binary signal value also change to the second binary value indicative of a direct connection between the inputs. Accordingly, an enhanced binary encoding is achieved by evaluating not only the binary signal value at the inputs, but also which inputs are connected together, the selective interconnection of inputs extending the 2.sup.N options available for conventional binary encoding.

Abstract: A description language and a parser generator for top-down parsers allows grammars for top-down parsers to be defined using a sequence of productions written as extended BNF expressions. For productions that are ambiguous, a lookahead construct in the grammar allows the programmer to specify an increased number of lookahead tokens. The lookahead construct can be specified on an expansion-by-expansion basis. As a result, the generated parser only maintains an increased number of lookahead tokens when required to process ambiguous productions.

Abstract: A system and method which displays a graphical icon, such as a slider bar, on a subscriber's television or display unit for indexing to different positions in a video stream in an interactive video delivery system. The interactive video delivery system preferably comprises at least one media server which stores one or more video streams, and one or more subscribers which each include a display device, such as a television. The television displays a slider bar or other graphical icon, and the slider bar is used to index to different locations in the video stream. During video delivery, the user may use or adjust a knob on the slider bar, preferably using a remote control device, to indicate a desire to "jump" to a different location in the movie or video stream. The media server receives the slider bar user input from the subscriber device and begins outputting the normal play stream at the desired position.

Abstract: An apparatus and method of efficiently and dynamically generating the addresses associated with a set of instructions in a microprocessor pipeline is disclosed. Program counter age bits associated with the offsets of an address of a predetermined instruction within a set of instructions are used to indicate the chronological age of each instruction within the set of instructions. The age bits are generated by a logic circuit which also dispatches instructions to various execution units. The age bits are used to maintain and track the addresses of an instruction stream within a processing system so that there is no need to store the addresses of each and every instruction.

Abstract: In a program data stack in a computer system, every stack is implemented as two substacks, one to contain references and one to contain primitive data. In this manner, whether a piece of information on a stack is a reference or a primitive value is easily determined according to which substack it resides in. Each substack is itself a full-fledged stack data structure with a stack base, a stack pointer, and a stack limit. In the preferred embodiment, there is also a frame pointer for each substack. The normal instruction set is modified so that instructions that operate with references use the reference stack whereas instructions that operate with data use the primitive data stack. Specifically, during compilation, or loading, all instructions which can operate indiscriminately with either references or data are replaced by equivalent, but reference-specific or data-specific instructions.

Abstract: The present invention is a method and apparatus for providing instrumentation of procedure calls in dynamically linked environments. More specifically, an embodiment of the present invention includes an API that allows a user to define procedures that are called during specific times during the execution of a runtime linker. By defining procedures in accordance with this API, the user can select procedures within a user program for auditing. The API also allows the user to define an entry procedure that will be called immediately before each audited procedure and an exit procedure that will be called immediately after each audited procedure. The runtime linker uses the procedures defined by the user to select procedures within the program for auditing. The runtime linker then arranges for the entry procedure to be called before, and the exit procedure to be called after, each audited procedure.

Abstract: A flexible scheme is provided for designating the appropriate write-back protocol best suited for each memory level within a multi-level-cache computer system. The skip-level memory hierarchy of the present invention includes a lower-level copy-back cache and a higher-level write-through cache. This greatly simplifies the implementation of the higher-level cache, since it may be implemented with a write-or-read access to its address tag. Although counterintuitive, a write-through higher-level cache in a distributed shared memory may also increase the efficiency of the computer system without unduly increasing the volume of network traffic within the computer system. This is because a write-through higher-level cache increases the probability of readily-available cached copies of updated data which are consistent with the home copies of the data, thereby reducing the number of fetches from remote home locations whenever the data is not found in the lower-level cache but is found in the higher-level cache.

Abstract: The present invention is directed to checking and reducing an intermediate result signal arising from a manipulation of data signals without using conditional branches, thereby improving instruction processing in a superscalar pipelined processor. In the preferred embodiment of the present invention, the data signals are represented as signed 8-bit binary values in a two's compliment format. This requires that the intermediate result signal be stored in a register that is greater than 8-bits wide to allow for the proper checking of an overflow condition. It is presently contemplated that the present invention include using a processor operating under program control with the program having the following operations. The program determines whether the intermediate result signal is in a positive overflow state or a negative overflow state. The program sets a first mask signal to have 8 lower bits in an OFF position when the intermediate result signal is inside the range of a signed 8 bit integer.

Abstract: A staticized flop circuit converts a dynamic signal appearing across the output of a logic circuit into a static signal, and includes a dynamic-to-static convertor which minimizes glitching in the static output. The dynamic-to-static convertor includes a pull-down device, operatively coupled between an output node and a ground, which is closed while an input node is at a precharge potential and which is open while the input node is at a ground potential, and a pull-up device, operatively coupled between a source voltage and the output node, which is closed while the input node is at the ground potential and which is open while the input node is at the precharge potential.