Abstract: A sliding panel configured along an edge of a GUI is associated with an application. When a panel activation event occurs, the panel slides into view, allowing the user to view the information generated by the application and to interact with the configured application. The panel automatically closes when a panel deactivation event occurs. Multiple panels can be attached to each edge of the GUI. The GUI is maintained such that the GUI representation of the sliding panel is always visible and accessible in a first portion of the GUI. A second portion of the GUI can be used to display workspace output. The content of the first portion of the GUI remains constant as a user switches from one workspace to another. The content of the first portion of the GUI therefore remains accessible from any workspace.

Abstract: A method of improving the timing performance of a circuit includes the step of producing a first set of timing results from a static timing analyzer operating on a netlist that characterizes a circuit. A critical timing path within the circuit is then identified from the first set of timing results. The critical timing path is then converted into an equivalent schematic circuit representation. A simulation of the equivalent schematic circuit representation on a circuit simulator produces a second set of timing results. Timing discrepancies are then located between the first set of timing results and the second set of timing results. Based upon the timing discrepancies, cells are substituted into the critical timing path to improve the timing performance of the critical timing path.

Abstract: A method for coupling a linear impedance control (LIC) type output driver to IEEE 1149.1 boundary scan circuitry includes entering a boundary scan load mode to load a test pattern into a chain of boundary scan registers (BSRs). The test pattern includes values corresponding to output enable and data signals according to the IEEE 1149.1 standard. Then these data and output enable signals from the BSRs are converted into test "q.sub.-- up" and "q.sub.-- dn" signals meeting the requirements of the LIC driver. These test "q.sub.-- up" and "q.sub.-- dn" signals are selectively provided to the LIC driver during boundary scan testing of the LIC driver. In a further refinement, the method enters a boundary scan capture mode to capture the response (i.e., the functional q.sub.-- up and q.sub.-- dn signals) of the circuit under test to input test patterns shifted into the BSRs. The functional q.sub.-- up and q.sub.-- dn signals are converted into response data and oe signals complying with the IEEE 1149.

Abstract: Various components of a color pixel stored in an accumulation buffer and respective components of a color pixel in a frame buffer are processed substantially simultaneously in partitioned multiplication operations and partitioned addition operations. An accumulation buffer weight is substantially multiplied by each component of the buffer pixel substantially simultaneously in a partitioned multiplication operation. The weighted buffer pixel is adjusted in some embodiments to effectively increase the range of accumulation buffer weights which can be effectively processed by the processor. For example, the weighted buffer pixel is doubled to effectively extend the effective range of the accumulation buffer weight from approximately -0.5 to 0.5 to at least the range of approximately 0.0 to approximately 1.0.

Abstract: A write barrier to stores into a partially relocated large or popular memory object facilitates bounded pause time implementations of relocating garbage collectors, including e.g., copying collectors, generational collectors, and collectors providing compaction. Such a write barrier allows a garbage collector implementation to interrupt relocation of large or popular memory objects so as to meet bounded pause time guarantees. A partially relocated object identifier store including "copy from" identifier storage accessible to write barrier logic allows the write barrier logic to maintain consistency between FromSpace and ToSpace instances of a partially relocated memory object. "Copy from" identifier storage allows the write barrier logic, or a trap handler responsive thereto, to broadcast a store-oriented memory access targeting the FromSpace instance to both FromSpace and ToSpace instances.

Abstract: A method and apparatus for publishing and receiving events to a network. A plurality of "publisher" entities publish information and a plurality of "subscriber" entities request and use the information. Publishers and subscribers are connected to each other through a network. The network is a "store and forward" network whose routing is "content-based." The basic quanta of information is called an "event." Publishers publish events and subscribers subscribe to events that match criteria defined by the subscriber. Publication and subscription are performed asynchronously. Publishers and subscribers do not have direct knowledge of each other. The system receives a published event from a publisher and routes the event to all appropriate subscribers. Each subscriber is guaranteed to receive all events published on the system if, and only if, they match the subscription criteria specified by the subscriber.

Abstract: An innovative method and system of performing multiway branch operations on a microprocessor architecture which supports single instruction multiple data (SIMD) operations is provided. A computer processor includes a branch condition register, a graphic status register, a displacement register, a branch offset register, a program counter register and circuit logic responsive to a multiway branch opcode. Bitwise AND logic coupled to the branch condition register and the graphic status register performs a bitwise logical AND between a mask contained in the branch condition register and multiple comparison results contained in the graphic status register. An output port from bitwise logical AND is coupled to a constant array and selects a set of constant values based on the bitwise logical AND result value.

Abstract: A method in a computer network having a first plurality of nodes coupled to a common network infrastructure and a distributed shared memory distributed among the first plurality of nodes for servicing a first memory access request by a first node of the computer network pertaining to a memory block having a home node different from the first node in the computer network. The computer network has no natural ordering mechanism and natural broadcast for servicing memory access requests from the plurality of nodes. The home node has no centralized directory for tracking states of the memory block in the plurality of nodes. The method includes the step of receiving via the common network infrastructure at the home node from the first node the first memory access request for the memory block.

Abstract: A partially relocated object identifier store including "copy from" identifier and "copy to" identifier storage accessible to write barrier logic allows the write barrier logic to maintain consistency between FromSpace and ToSpace instances of a partially relocated memory object without software trap handler overhead. Optional "How far" indication storage facilitates differentiation by the write barrier logic between a copied portion and an uncopied portion of the partially relocated memory object. An optional "mode" indication facilitates differentiation by the write barrier logic between a copy phase and a pointer update phase of relocation by the garbage collector implementation. In some embodiments, pointer update and copying phases may overlap. "Copy to" identifier storage facilitates broadcast of a store-oriented memory access to the FromSpace instance to both FromSpace and ToSpace instances.

Abstract: A collision avoidance system for a plurality of vehicles equipped with GPS receivers, each broadcasting current location information to other vehicles and receiving and displaying location information from other vehicles, enables a vehicle operator to be aware of the location of the other vehicles. For vehicles not equipped with GPS, and transceivers, information about location is taken from common ground control equipment such as an FAA control station and broadcast to all vehicles. In an aircraft environment, flight plans can be filed and closed out automatically.

Abstract: Circuits and methods of testing an integrated circuit die are disclosed. Active logic setting circuits are incorporated into input cells of a die. During testing, the active logic setting circuits weakly drive the input cells to a definite logic level. Therefore, the necessity of connecting probes to all of the input pads to prevent floating signals in the die is eliminated. Furthermore, during normal operations the active logic setting circuits have little or no effect on the performance of the die.

Abstract: A platform-independent, usage-independent, location-independent quote configuration system is described. The present invention, operating in a computer network, is a quote configurator comprising, 1) a client module, the client module having a platform-independent user interface for receiving quote input and command selections from a user, the quote input and command selections including product selection and selection of information indicative of business rules, and 2) a server coupled to the client module across the network, the server having access to quote data and business rules, the server including a platform-independent server interface configured to receive the quote input and command selections from the client module, the server validating the quote input based on the quote data and the business rules.

Abstract: A memory circuit which steers read/write data to a memory array including a plurality of columns (at least one of which is redundant). Coupled to the bit line of each column are a normal mode write transistor and a redundant mode write transistor. If a failing column is detected during manufacturing testing of the memory array, a repair signal for each of the failing column and subsequent columns in the array are de-asserted. When a write operation is performed on the array, an input data bit is provided corresponding to each non-redundant column in the array. The input data bit written to a particular bit line, however, depends upon the state of the repair signal for that column. If the repair signal for a particular column is asserted, the input to the normal mode write transistor is conveyed as write data. Conversely, the input to the redundant mode write transistor is conveyed as write data if the repair signal is de-asserted for a particular column.

Abstract: A method and apparatus for publishing and receiving events to and from a network. A plurality of "publisher" entities publish information and a plurality of "subscriber" entities request and use the information. Publishers and subscribers are connected to each other through a network. The network is a "store and forward" network whose routing is "content-based." The basic quanta of information is called an "event." Publishers publish events and subscribers subscribe to events that match criteria defined by the subscriber. Publication and subscription are performed asynchronously. Publishers and subscribers do not have direct knowledge of each other. The system receives a published event from a publisher and routes the event to all appropriate subscribers. Each subscriber is guaranteed to receive all events published on the system if, and only if, they match the subscription criteria specified by the subscriber.

Abstract: The present invention is directed to checking and reducing an intermediate signal arising from a manipulation of 16-bit signed data signals without using conditional branches, thereby improving instruction processing in a superscalar pipelined processor or an arithmetic unit that can execute several arithmetic operations concurrently. In the preferred embodiment of the present invention, the data signals are represented as signed 16-bit binary values in a two's compliment format. An intermediate register is used to hold the intermediate signal which is greater than 16-bits in width to allow for the proper checking of an overflow condition. It is presently contemplated that the present invention include using a processor operating under program control. The program determines whether the intermediate signal is in a positive or negative overflow state.

Abstract: A single transaction technique for a journaling file system of a computer operating system in which a single file system transaction is opened for accumulating a plurality of current synchronous file system operations. The plurality of current synchronous file system operations are then performed and the single file system transaction closed upon completion of the last of the file system operations. The single file system operation is then committed to a computer mass storage device in a single write operation without the necessity of committing each of the separate synchronous file system operations with individual writes to the storage device thereby significantly increasing overall sytem performance. The technique disclosed is of especial utility in conjunction with UNIX System V based or other journaling operating systems.

Abstract: In a compression system, three-dimensional geometry is first represented as a generalized triangle mesh, a data structure that allows each instance of a vertex in a linear stream to specify an average of two triangles. Individual positions, colors, and normals are quantized, preferably quantizing normals using a novel translation to non-rectilinear representation. A variable length compression is applied to individual positions, colors, and normals. The quantized values are then delta-compression encoded between neighbors, followed by a modified Huffman compression for positions and colors. A table-based approach is used for normals. Decompression reverses this process. The decompressed stream of triangle data may then be passed to a traditional rendering pipeline, where it is processed in full floating point accuracy.

Abstract: A computer implemented method and computer system for testing a target software product is presented. The method includes constructing a finite state machine in which portions of the target product are ascribed to states of the state machine. The state machine may correspond to a predetermined test case for the target software product. A number of state functions are provided, each of the state functions performing at least one verification on the target software product. The state functions also may include transitioning from one state to the next, for example, by a "next window" a "previous window" action if the target software program is a windows based program. The state functions may also verify that a current state in which the state machine exists is a correct state, may verify information that is supposed to have been written to a memory is written in fact to the memory, and may verify that the path to the information is correct.