Abstract: A non-blocking multiple-phase clocking system for use with dynamic logic provides clock phases with overlapping evaluation phases to a circuit including a several cascaded dynamic logic gates. The circuit also includes a first flip-flop that is coupled to provide input signal(s) to the first dynamic logic gate of the cascade and a second flip-flop that is coupled to receive output signal(s) from the last dynamic logic gate of the cascade. Through the use of the overlapping evaluation phases and proper assignment of the clock signals to the dynamic logic gates, the output signal(s) generated by the dynamic logic gates receiving a particular clock phase are used as input signals to the dynamic logic gates receiving the next clock phase. Because of the overlapping of the clock phases, no latch is used. The clock phases are assigned to a particular dynamic logic gate so that the this dynamic logic gate enters the evaluation phase before the input signal(s) to the particular dynamic logic gate arrives (i.e.

Abstract: A computer-implemented method and apparatus in a computer system for inter-process communication. A first procedure allocates a first buffer in a first memory space shared by the first procedure (e.g. a client process) and a second procedure (e.g. a kernel or server process). The first procedure then marshals arguments for communicating with the second procedure in the first buffer. The first procedure indicates that a message for the second procedure is being passed and passes a first reference to the first buffer in the first memory space to the second procedure. The second procedure detects the indication of the message by the first procedure. The second procedure then references the first buffer and copies the arguments contained in the first buffer into a temporary buffer. The second procedure can then deallocate the first buffer.

Abstract: An integrated circuit and associated method for reducing total signal propagation delay as well as power consumption and thermal dissipation. The integrated circuit comprises a plurality of active layers coupled together in close proximity. In order to produce the integrated circuit, at least two active layers are removed from their respective substrate after integrated circuit processing. Some of the methods that may be used include Silicon on Insulator ("SOI") and epitaxial etch stop ("EES") processes. After removal of the active layers, at least one via is implemented on a bottom surface of each active layer in order to establish a mechanical and electrical connection between the via and its associated metal interconnects. Thereafter, the active layers are coupled together by ultrasonic welding or through nitride lamination using Titanium Nitride for conductive regions and Silicon Nitride for insulative regions.

Abstract: A computer system including one or more processing nodes, each of which includes one or more subnodes is provided. One of the subnodes (the controller subnode) manages the interface between the processing node and the remainder of the computer system. Other subnodes (snooper subnodes) are employed to store access rights for coherency units within the memory. The processing node's memory is logically divided into portions, and each subnode stores access rights for a particular memory portion. When a transaction is initiated within the processing node, the subnode storing the access rights for the coherency unit affected by the transaction analyzes the access rights and determines if the transaction may complete locally within the processing node. If coherency activity is required, the subnode asserts an ignore signal causing the transaction to be omitted while coherency activity is performed to acquire sufficient access rights.

Abstract: A method and apparatus for rendering an object or scene from a preselected viewpoint onto a display. The object is represented by a texture map stored in a memory of a processor-based system, and the viewpoint is represented by geometry data stored in the memory. The viewpoint on the object may be represented in the geometry data a polygon (or more than one polygon). The processor determines span data by edge-walking the polygon, and transfers the span data to the memory controller. Beginning with a first such span, the processor then transfers the span data (one span at a time) to the memory controller. After each such transfer, the memory controller takes over execution of the rendering procedure, beginning with mapping the current span onto a span of voxels (volume elements) in texture map space. The memory controller then retrieves the colors and textures for that span, and renders the span accordingly (i.e. either displays it or writes it to an appropriate memory).

Abstract: A power sequence controller contains wakeup logic for responding to each wakeup event signal intercepted by the power sequence controller. The wakeup logic compares the intercepted wakeup event signal with a wakeup filter mask to determine if the wakeup event signal should be processed or ignored. If the wakeup event signal requires processing, the wakeup logic transitions the system's processor to a working state. The wakeup logic also determines if the intercepted wakeup event signal requires software processing. If so, a non-zero value associated with the wakeup event signal is stored in an interrupt source register, which causes the processor to execute an interrupt handler procedure and process the wakeup event signal when it transitions to a working state. The wakeup logic also evaluates the processor sleep state to determine if transitioning the processor from the sleep state to a working state requires execution of a processor wakeup procedure to return the processor to normal operation.

Abstract: Apparatus that provides additional flexibility for a computer interface that serves two computer subsystems, when at least one of these subsystems undergoes a change, such as a new version, a change in subsystem functionality, or fixing of a "bug." An interposer, positioned between a first interface for a first computer subsystem and a second subsystem interface for a second computer subsystem, monitors command or data request signals and response signals generated in the first subsystem and passing to the second subsystem through the second subsystem interface and tests these signals for recognition by, consistency with and compatibility with, the second subsystem, given the change(s) that have been made in the first computer subsystem.

Abstract: A data compare technique for detecting memory errors on a computer's memory subsystem is disclosed. The technique simulates memory intensive software to determine if memory errors occur when the computer's memory subsystem is subjected to heavy memory usage. The technique copies an extensive test file, performs checksums of the original and copied test files and compares the checksum of the original file to the checksum of each copied file to identify checksum differences. The checksum differences indicate the occurrence of a memory error.

Abstract: A system for screening data packets transmitted between a network to be protected, such as a private network, and another network, such as a public network. The system includes a dedicated computer with multiple (specifically, three) types of network ports: one connected to each of the private and public networks, and one connected to a proxy network that contains a predetermined number of the hosts and services, some of which may mirror a subset of those found on the private network. The proxy network is isolated from the private network, so it cannot be used as a jumping off point for intruders. Packets received at the screen (either into or out of a host in the private network) are filtered based upon their contents, state information and other criteria, including their source and destination, and actions are taken by the screen depending upon the determination of the filtering phase. The packets may be allowed through, with or without alteration of their data, IP (internet protocol) address, etc.

Abstract: A microprocessor is configured to generate help instructions in response to a data cache miss. The help instructions flow through the instruction processing pipeline of the microprocessor in a fashion similar to the instruction which caused the miss (the "miss instruction"). The help instructions use the source operands of the miss instruction to form the miss address, thereby providing the fill address using the same elements which are used to calculate cache access addresses. In one embodiment, a fill help instruction and a bypass help instruction are generated. The fill help instruction provides the input address to the data cache during the clock cycle in which the fill data arrives. The appropriate row of the data cache is thereby selected for storing the fill data. The bypass help instruction is dispatched to arrive in a second pipeline stage different from the stage occupied by the fill help instruction.

Abstract: In brief summary, the invention provides a new message packet transfer system, which may be used in, for example, a multiprocessor computer system. The message packet transfer system comprises a plurality of switching nodes interconnected by communication links to define at least one cyclical packet transfer path having a predetermined diameter. The switching nodes may be connected to, for example, digital data processors and memory to form processing nodes in an multiprocessor computer system, and/or to other sources and destinations for digital data contained in the message packets. The switching nodes transfer message packets each from a respective one of the switching nodes as a respective source switching node to a respective one of the switching nodes as a respective destination switching node.

Abstract: In a processor that executes complex instructions which are expanded into microinstructions prior to execution, non-complex instruction execution is optimized by providing a by-passable helper logic for expanding complex instructions into microinstructions. Control logic parses a bundle of instructions into sub-bundles of non-complex instructions and sub-bundles of microinstructions. The control logic detects when a complex instruction is present in a bundle of instructions and directs the complex instruction to the helper logic for expansion into two or more microinstructions. Each non-complex instruction bypasses the helper logic, thereby improving the execution performance of the non-complex instruction.

Abstract: A method and apparatus for generating a qualify bit and detecting matching addresses in the completion unit register file, or annex, of a processor. A qualify bit is appended to each entry in the annex. Overlapping register windows are represented by a window pointer and a register index. Annex entries addressed to the same window or addressed to GLOBAL registers always qualify. Annex entries addressed to OUT registers only qualify if the instruction address is one of the IN registers of the next window. Annex entries addressed to IN registers only qualify if the instruction address is one of the OUT registers of the previous window. A pseudo-address bit is appended to each annex entry. For IN and OUT registers, the indexes for the aliases differ by one bit. The pseudo-address bit normally takes on the value of the most significant bit of the annex entry's index.

Abstract: A dictionary system has a vendor computer and a plurality of client computers that communicate through the Internet. Each client computer has a word processor program with a spelling checker that utilizes a local main dictionary provided by the vendor and a local customized dictionary containing words added by the user. The vendor computer contains a dictionary of approved words, a database of misspelled words, and a database of requested words. When a user adds a new word to the local customized dictionary, an Internet request is sent to the vendor computer to add the new word to the dictionary of approved words. The user is notified by an Internet message from the vendor computer if the requested word is misspelled. The database of requested words from all users is reviewed periodically and utilized to update the approved dictionary. The updated dictionary is periodically released to the users as an upgrade to the local main dictionary.

Abstract: A 3-D graphics accelerator which includes a command block or preprocessor, a plurality of floating point processors or blocks, and one or more draw processors or blocks. The 3-D graphics accelerator includes a plurality of direct data channels or point-to-point buses, collectively referred to as the CF bus, which connect the command preprocessor to each of the plurality of floating point processors. The 3-D graphics accelerator also includes a plurality of direct data channels or point-to-point buses, collectively referred to as the FD bus, which connect the plurality of floating point processors to each of the draw processors. The system of the present invention also implements a bus from the command preprocessor directly to the draw processors, referred to as the CD bus, which uses portions of the above direct data channels. The CD bus shares or "borrows" the data lines from the CF bus a id the FD bus and uses the floating point processors as buffer chips.

Abstract: A combination heating and cooling apparatus which comprises a compartment into which an item to be heated or cooled may be placed; an electromagnetic wave generator; wherein during a first mode of operation of the apparatus, the electromagnetic waves are directed into the compartment to heat the item; at least one sorber having a housing defining an enclosure; a sorbate/sorbent compound located within the enclosure; a waveguide for coupling electromagnetic waves generated by the electromagnetic wave generator to the sorber; wherein electromagnetic waves transmitted by the electromagnetic wave generator are propagated through the enclosure to desorb the sorbate from the sorbate/sorbent compound; a condenser connected to the sorber; an evaporator connected to both the condenser and the sorber and positioned in heat exchange relation with the compartment; and a controllable valve interposed between the condenser and the evaporator; wherein sorbate which is desorbed in the sorber is condensed in the condenser and

Abstract: A method and apparatus for synchronizing objects is provided. A cache of synchronization constructs is provided and used to synchronize a thread with an object. A free list contains synchronization constructs not allocated to synchronize an object. A synchronization construct is allocated when at least one thread requests synchronization with an object. In response to detecting a collection enabling condition, synchronization constructs allocated to objects not synchronized with any thread are deallocated. A local hash table is assigned to each thread. The local hash table contains synchronization constructs used to synchronize objects to the thread to which the local hash table is assigned.

Abstract: An arbiter circuit having a plurality of mutual exclusion (MUTEX) elements is disclosed. Each of the MUTEX elements is coupled to receive a different combination of request signals and their complements and grant signals and their complements fed back from the output of the arbiter circuit. At any point in time, only one of the plurality of MUTEX elements is selected based on the current state of the grant signals. The selected MUTEX element is used to arbitrate and grant one user exclusive access to a shared resource among the one or more users requesting exclusive access to the shared resource. All the other MUTEX elements in the arbiter circuit are disabled and are inactive during this time. After issuing the grant signal, the selected MUTEX element is disabled and a new MUTEX element responsible for issuing the next grant signal is selected based the new state of the grant signals.

Abstract: An on-chip cache memory is used to provide a high speed access mechanism to frequently used channel state information for operation of a DMA device that supports multiple virtual channels in a high speed network interface. When an access to a particular channel state is performed, e.g., by a host processor or the DMA device, the cache is first accessed and if the state information is not located currently in the cache, external memory is read and the state information is written to the cache. As the cache does not store all the states stored in external memory, replacement algorithms are utilize to determine which channel state information to remove from the cache in order to provide room to store a recently accessed channel. A doubly linked list is used to track the most recently used channel. As cached channel information is accessed, the corresponding entry is moved to the top of the list. The doubly linked list provides a rapid apparatus and method for updating pointers to the cache.