Abstract: A method and apparatus for optimizing cost-based heuristic instruction scheduling for a pipelined processor is disclosed which has particular application to compile time instruction scheduling after code generation. Instruction scheduling is optimized by determining the optimal weights to be used by an apparatus for cost based heuristic instruction scheduling for a particular pipelined processor. The optimal weights are determined based on the lowest of the lowest costs incurred by different collections of interrelated weight sets. Each collection of interrelated weight sets comprises a randomly generated initial weight set and subsequent interrelated weight sets generated in a predetermined manner. The predetermined manner for generating subsequent weight sets facilitates rapid identification of the optimal weight set for a collection, and thereby rapid identification of the overall optimal weight set for the collections.

Abstract: A substrate, a heat slug with an access cavity, a lid, and a heat sink having a stem are used to package a high applied power VLSI die. The substrate comprises a stepped housing cavity at its center, and a number of electrical contacts disposed at its underside. The inactive side of the high applied power VLSI die, the top surface and underside openings of the stepped housing cavity of the substrate, the heat slug including its access cavity, the stem of the heat sink, and the lid are coordinated in their sizes and geometric locations in view of the applied power and the heat transfer efficiency of the heat sink.

Abstract: A bus-to-bus interface preserves data coherence between masters and slaves operating within a multiple processor computer system. Two buses are connected via the interface. The first bus connects a number of self-identifying masters. The second bus connects a number of master devices and a number of slave devices. The second bus has no mechanism with which devices connected to the second bus may identify themselves. The interface contains a pair of registers for each slave device connected through the second bus. One register stores a busy bit if the corresponding slave is engaged on behalf of a master. The second register stores an identifying code for the master delegating a task to the corresponding slave. When a slave has accepted a task on behalf of a master and commanded the master to relinquish the bus, the busy register will be set and the master identification register will store the identifying code for the delegating master.

Abstract: A method and apparatus for interprocess message switching between a sender process and a plurality of receiver processes is disclosed. Messages supported comprise request and notice messages. Receiver processes supported comprise handler processes and observer processes. Request messages may be observed as well as handled, and notice messages may be handled as well as observed. Handler and observer processes may be non-executing as well as executing. Sender processes do not need to specify the identity of the receiver processes. The sender process and the receiver processes may be executed on the same computer or on two or more computers in a network.

Abstract: An apparatus and method are disclosed for switching the context of state elements of a very fast processor within a clock cycle when a cache miss occurs. To date, processors either stay idle or execute instructions out of order when they encounter cache misses. As the speed of processors become faster, the penalty for a cache miss is heavier. Having multiple copies of state elements on the processor and coupling them to a multiplexer permits the processor to save the context of the current instructions and resume executing new instructions within one clock cycle. The invention disclosed is particularly useful for minimizing the average instruction cycle time for a processor with a main memory access time exceeding 15 processor clock cycles. It is understood that the number of processes who's states are duplicated may easily be a large number n.

Abstract: An intelligent cache memory system and associated method for reducing a central processing unit (CPU) idle time. The system performs prefetches based on data fetching characteristics of the CPU. The system includes cache control logic, a first and a second cache memory, each having a number of cache lines, and a first and a second cache tag array, each having cache tag entries corresponding to the cache lines. The cache tag entries comprise cache tags and valid bits. The cache tag entries of the second cache tag array further comprise interest bits. In addition to their traditional functions, the cache tags and the valid bits, in conjunction with the interest bits, are used to track the data fetching history of the CPU. For each read cycle, the cache control logic returns the data being fetched by the CPU from either the first or the second cache memory or the main memory. Additionally, the cache control logic initiates prefetch and updates the data fetching history conditionally.

Abstract: A computer system includes first and second processors each having a virtual cache memory, a main memory, a bus coupled to the main memory and the processors, and apparatus for addressing the cache associated with each processor for providing that the data in each virtual cache stores data from the same physical location in main memory at a same index position in each virtual cache, a memory management unit (MMU) coupled to each processor such that addressing information is transferred to each memory management unit to indicate the virtual address of data to be written to the virtual cache, the memory management unit generating from the virtual address a physical address, and determining whether any other virtual cache includes data from the same physical memory positions.

Abstract: A test driver generator is provided for generating test drivers from test function designations and attribute value specifications of software interfaces. For each set of designations and specifications for a software interface, the test driver generator generates a test driver. The test driver executes the designated test functions selectively based on selections provided at its invocation, using the selected combinations of attribute values specified. For each selected combination of attribute values of each selected test function, the test driver creates the test data for the particular combination of attribute values, executes the selected test function and deletes the created test data. The test driver repeats the process for all selected combinations of attribute values of all selected test functions.

Abstract: In a network of object oriented distributed systems, a plurality of program code managers, each having access to a plurality of program code segment objects, a plurality of address space managers, each having access to a plurality of address space objects having linked program segment and symbol address information, and a plurality of trusted third party authentication managers are provided, thereby allowing a client process executing in non-supervisor mode to be able to dynamically link a program segment to either another program segment in another address space or a process in either another address space or the client's address space, without compromising the security of the systems.

Abstract: An auto-checking testing funtion generator is provided for generating auto-checking testing functions for procedures of a software interface from a formal specification specifying the procedures. The procedures are specified with procedure semantic expressions identifying the procedures and specifying their arguments, returning results, raisable exceptions, exceptional and normal terminations. Each exception or normal termination specifies the correct post-execution exception or normal termination state for the procedure given a particular pre-execution state. The procedure semantic expressions are boolean expressions constructed using comparison and boolean operators, calls to the procedure, auxiliary and special functions. The auxiliary functions are user supplied, and the special functions are supplied by the auto-checking testing funtion generator. An auto-checking testing funtion is generated for each procedure.

Abstract: A method and apparatus is disclosed for cooling a multi-chip module using embedded heat pipes. Semiconductor chips are disposed into the multi-chip module through cavities in the module substrate. The semiconductor chips engage heat pipes embedded within the substrate. The heat pipes conduct heat away from the semiconductor chips through a heat conductive bonding layer.

Abstract: A system and method is provided to perform quick patch level tests in a timely manner. The normal function of the patch is first computed using the convex hull property of the patch. The control points, which indicate the direction of the normals of the normal function, are used to construct a floating cone. This cone contains all the normals to the given patch. The floating cone is then moved in space and is truncated by two parallel planes orthogonal to the cone axis to contain the original given patch. From this information, frontfacing and backfacing volumes are constructed. These volumes are then used to derive information about the patch that can speed up its processing. For example, culling may be performed on the patch level before tessellation into triangles. The time consuming operations of computing normals and the floating cone are performed at the creation time of the patch and are view independent.

Abstract: In a computer system, a system boot prom having a bootstrap program is provided for booting the computer system from a boot device having a boot program and an operating system. The bootstrap program is designed to create a boot prom interface through which the boot program uses to locate the device driver for loading the operating system from the boot device. As a result, the device driver for the boot device may be provided in the system boot prom or a third party boot prom, thereby allowing the computer system to be booted from either a standard or a third party boot device without requiring rebuilding of the system boot prom.

Abstract: A high speed, low powered, BiCMOS TTL to CMOS translator circuit and method which relies on an internally generated reference voltage and which is capable of driving high loads. The translator circuit includes a first inverting and translating stage having a pull up transistor and a pull down transistor, a high gain stage and a second inverting stage.

Abstract: A cache array, a cache tag and comparator unit and a cache multiplexor are provided to a cache memory. Each cache operation performed against the cache array, read or write, takes only half a clock cycle. The cache tag and comparator unit comprises a cache tag array, a cache miss buffer and control logic. Each cache operation performed against the cache tag array, read or write, also takes only half a clock cycle. The cache miss buffer comprises cache miss descriptive information identifying the current state of a cache fill in progress. The control logic comprises a plurality of combinatorial logics for performing tag match operations. In addition to standard tag match operations, the control logic also conditionally tag matches an accessing address against an address tag stored in the cache miss buffer.

Abstract: In a memory system having a main memory and a faster cache memory, a cache memory replacement scheme with a locking feature is provided. Locking bits associated with each line in the cache are supplied in the tag table. These locking bits are preferably set and reset by the application program/process executing and are utilized in conjunction with cache replacement bits by the cache controller to determine the lines in the cache to replace. The lock bits and replacement bits for a cache line are "ORed" to create a composite bit for the cache line. If the composite bit is set the cache line is not removed from the cache. When deadlock due to all composite bits being set will result, all replacement bits are cleared. One cache line is always maintained as non-lockable. The locking bits "lock" the line of data in the cache until such time when the process resets the lock bit.

Abstract: The invention is an object-oriented graphic user interface for use in computer controlled display systems, and in particular, display systems having object oriented graphic interfaces. A central processing unit (CPU) is provided and is coupled to a display for displaying graphic and other data. The CPU is further coupled to a cursor control device which permits a user to selectively position a cursor at a desired location on the display, and signal the CPU of selections in accordance with the teachings of the present invention. Buttons are generated by the CPU and displayed which correspond to either a single function to be executed by the CPU, or a button stack which has associated therewith a plurality of functions disposed on a menu. The menu includes a plurality of buttons and/or button stacks. A button stack may be provided with a default function which is automatically executed by the CPU when a predetermined signal is provided by the user through the cursor control device.

Abstract: A method and apparatus for improving the testability of system logic of an integrated circuit having embedded memory arrays is disclosed. The embedded memory arrays are coupled to a binary constant generation and selection circuit which is also coupled to the system logic. During a test mode, the selection circuit sends a binary constant to the system logic in lieu of normal operational data output from the memory arrays. The system logic is tested while the binary constant is continuously applied.