Abstract: A command preprocessor is disclosed that translates geometry input data from differing formats into a standard format for accelerated rendering. The command preprocessor contains a set of reformatting control registers that are preprogrammed with translation parameters by a host processor. The translation parameters in the reformatting control registers specify translation operations.

Abstract: Constrained resource allocation techniques are implemented with a digital computer due to its improved speed and graphics capability. These techniques allow for rapid resource constrained scheduling when given a precedence ordered list of activities. Resources are allocated to activities in order of highest priority with all precedence constraints being taken into account. Resources are allocated in such a manner that preserves the integrity of the random variables associated with start and finish times of activities. Activity durations and start/finish expected values and variances are adjusted to account for shortfalls occurring prior to an activity's start time and between an activity's start and finish times. The result is a schedule of start and finish times for each activity that is resource feasible and achievable within a prescribed confidence level.

Abstract: A computer graphics interface between an application program and device pipeline. The computer system implements a view model including a plurality of coordinate systems. An acyclic graph is stored, wherein the acyclic graph representing dependencies between various items in each of the plurality of coordinate systems. Upon a creation of an item in a first coordinate system of the plurality of coordinate systems, an object is associated with the item an object which associates all derived items from the item in others of the plurality of coordinate systems, wherein the object includes a first flag for indicating whether the item current item is valid within the first coordinate system. The object further includes a second flag for indicating that at least one of the derived items is not valid in its respective coordinate system.

Abstract: A central processing unit of a computer system which has an arithmetic logic unit, a register file, an instruction decode/fetch instruction data unit, a bus interface, a multiplexer and a stall cache. The stall cache is coupled to the instruction decode/fetch instruction data unit by a data bus and an internal instruction bus, so that the stall cache can receive and store instructions that have been delayed by an external data fetch during a load or store operation. Upon the next data access, the stall cache allows the delayed instruction to be accessed by the internal instruction bus and to then be processed by the central processing unit without the delay of an external data fetch.

Abstract: A method and apparatus for extensible inter-application link management is disclosed. The apparatus is independent of the applications that manipulates the anchors linked by the links being managed. Anchors linked may reside on the same or different computers on a network. Links managed comprise navigation links and include links. Links managed may be further extended with application defined links. Application defined links may or may not require support by additional application provided link maker programs. Application defined links may inherit linking operations managed from the navigation link, include link and other existing application defined links with or without override.

Abstract: A test mode read back function for verifying the functions of the memory display interface and a VRAM frame buffer coupled to the memory display interface, wherein the memory display interface implements programmable pixel rates and pixel depths, and programmable pixel processing functions.

Abstract: A row select circuit for semiconductor memories is disclosed. The row select circuit includes a decoder portion and a driver portion. The decoder potion of the row select circuit includes a plurality of decoder circuits, each servicing a multiplicity of rows. Two levels of decoding are used to select a row. First, one of the plurality of decoder circuits is selected. Second, a predecoder is provided for simultaneously selecting one of the multiplicity of rows serviced by the selected decoder circuit. A single current source is used to service the multiplicity of rows associated with a particular decoder. The driver portion of the circuit includes a driver circuit for each row. Each driver includes an inverter stage, a driver stage, a clamp and a voltage reference circuit. For a selected row, the driver circuit provides ultra-fast access time. For the deselected rows, the driver circuit consumes minimal power.

Abstract: In a computer system requiring the CPU board to be installed and removed from the top of the chassis, there is included a CPU board installation and maintaining lever supported for movement from the base of the chassis and perpendicularly to the board when the board is installed. The board has an opening of a dimension to allow the board on installation and removal to passed over the lever into a position where contact with the lever will move the board into and out of its operative position without the need to use hardware on its installation and removal. Also included is a bracket having holding surfaces securing a speaker to the bracket and the bracket to the chassis, the latter holding surfaces allowing the bracket to assume a first position in the chassis and a second position away from the base of the chassis to create a suitable space for the installation and removal of the board to and from the chassis.

Abstract: Apparatus and methods for a cache controller to maintain cache consistency in a cache memory structure having a single copy of a cache tag memory while supporting multiple outstanding operations in a multiple processor computer system. The CPU includes a small internal cache memory structure. A substantially larger external cache array is coupled to both the CPU and the CC via first, integrated address and data bus. The CC is in turn coupled to a second bus interconnecting, among other devices, processors, I/O devices, and a main memory. The external cache is subblocked. A cache directory in the CC tracks usage of the external cache. An input buffer in the CC is connected to the first bus to provide buffering of commands sent by the CPUs. An output buffer in the CC is coupled to the second bus for buffering commands directed by the CC to devices operating on the second bus.

Abstract: The present invention is a method and apparatus for efficiently using existing cache memory in a virtual memory computer system for servicing different demands for such memory. Moreover, the method and apparatus of the present invention, provides a way for authenticating untrusted virtual memory managers (VMMs) and untrusted pagers, which use and supply such caching services. The method and apparatus for authenticating the VMM and pagers can be practiced in an object oriented programming environment or in a non-object oriented environment.

Abstract: The present invention operates within a data processing system with multiple DRAM memory modules, providing programmable memory timing through the use of a RAM within the memory controller unit of the data processing system. This RAM, termed the MCRAM, is used to store the timing information for memory operations. In particular, the MCRAM stores for each of the memory operations, Read, Write, and Refresh, the relevant information for RAS, CAS, LD, and AD timing signals. The presently preferred embodiment of the invention contemplates a particular programming process wherein the MCRAM is initially loaded with generic timing information which is acceptable to all possible DRAM memory modules. Following this loading operation, the processor obtains the ID number of the DRAMs within a particular memory module. This ID number is used in a look-up table to obtain the vendor-specific optimal timing for DRAMs corresponding to this ID number. The processor then writes this optimal timing information into the MCRAM.

Abstract: A head tracked stereo display system for generating virtual images over a wide range of viewer head movement, and for intermixing light from virtual objects and real objects in a natural arrangement. The system comprises a display device disposed within a base housing and a mirror coupled to rotate around the display device, such that the mirror transmits the stereo images to a viewer. A tracking system controls the angular position of the mirror to transmit the stereo images to the viewer as the viewer moves. To intermix the light from real and virtual objects, the image rendering system generates a z buffer for the real objects. The real objects are rendered with no color. A half silvered mirror is positioned to transmit the stereo images to the eyes of a viewer, and transmit light reflected from the real objects to the eyes of the viewer. An LCD array panel selectively blocks transmission of the light reflected from the real object.

Abstract: A film of elastomeric material is used to laminate the tape with LGA outer lead bumps to the stiffner plate of the semiconductor package. The elastomeric material has the necessary physical and electrical characteristics to provide the required firmness to maintain good electrical contact between the outer lead bumps and the corresponding contacting pads on a socket, ceramic substrate or PWB, and at the same time, to provide the required resilience to accommodate differences in heights between the outer lead bumps. The stiffner plate is fabricated with a cavity at its center for accommodating the VLSI die, and slots along the outer edges of its underside for storing the excess elastomeric material squeezed out when laminating the tape to the stiffner plate, thereby preventing the excess squeezed out elastomeric material from building up at the outer edges of the semiconductor package to a height in excess of the outer lead bumps.

Abstract: A method and apparatus is provided for testing self timed memory arrays which does not affect the state of cells within the arrays not being tested. Each memory array has a plurality of control, address and data registers which are coupled to the respective control, address and data lines into the memory array. A timing generator circuit receives an external clock pulse and provides the self-timed clock pulses to the memory array. During the shift mode, the control, address and data registers are chained together such that data for testing can be scanned serially into the registers. In order to prevent unplanned array modification operations from occurring during the shift mode because a bit shifted into the write-enable or clear register at the time a clock pulse derived from the timing circuitry is generated, a logic means is provided to disable all clock pulses during the shift mode.

Abstract: The bus of the present invention advantageously utilizes high-speed, source synchronized data transfers and lower-speed, globally synchronized transfers of arbitration and consistency information. In a first embodiment, a high speed clock signal and slower speed clock enable signal are globally distributed from a central arbiter to agents coupled to the bus. A sending agent utilizes the high speed clock signal for source synchronized data transfers by forwarding the high speed clock signal, along with the data, to one or more receiving agents. Thus, the globally distributed clock signal is used to accomplish source synchronized data transfers. Arbitration requests, by contrast, are processed at the slower clock enable signal rate in a globally synchronous fashion. In addition, by communicating data cycles information from the central arbiter to the receiving agent at the slower clock enable signal rate, the present invention avoids resynchronization and the possibility of metastability.

Abstract: A graphics accelerator is disclosed that achieves high performance at a relatively low cost by overcoming the variety of system constraints. The graphics accelerator comprises a command preprocessor for translating differing geometry input data formats into a standard format, a set of floating-point processors optimized for three dimensional graphics functions, and a set of draw processors that concurrently perform edgewalking and scan interpolation rendering functions for separate portions of a triangle.

Abstract: A data storage structure and its complementary selection data storage structure is provided with a complementary predictive annotation storage structure comprising a number of corresponding predictive annotation vectors, each having a number of predictive annotation tuples. To retrieve data from a data block tuple of a data vector, a data vector and its corresponding data selection and predictive annotation vectors are read out concurrently. Determination is made as to whether there is a selection hit and a prediction hit. Concurrently, one of the predictive annotation tuples is selected and recorded for the next access based on the predictive annotation selected and recorded in the previous access. Also concurrently, a data block tuple is selected based on the predictive annotation selected and recorded in the previous access, and a data element is selected from the selected data block tuple based on the access key, without waiting for the determination results.

Abstract: A computer system consisting of a host processor, memory and peripheral devices coupled via a bus which provides emulation of a microprocessor by coupling the microprocessor to the bus. The host processor provides emulation of microprocessor peripherals such that a microprocessor based system is supported and executes processes. A takeover mechanism is provided to enable the host processor to temporarily takeover the microprocessor to perform certain tasks. The host processor causes an interrupt to occur in the microprocessor and monitors the bus cycles initiated by the microprocessor to determine when the microprocessor performs fetches of the routine to service the interrupt. The host processor intercepts fetches for information regarding the location of the interrupt service routine and provides information that causes the microprocessor to execute code of a process to be executed during the takeover. For example, during the takeover, noninvasive debugging of the microprocessor can be performed.