Abstract: A test driver generator is provided for generating test drivers from test function designations and attribute value specifications of software interfaces. For each set of designations and specifications for a software interface, the test driver generator generates a test driver. The test driver executes the designated test functions selectively based on selections provided at its invocation, using the selected combinations of attribute values specified. For each selected combination of attribute values of each selected test function, the test driver creates the test data for the particular combination of attribute values, executes the selected test function and deletes the created test data. The test driver repeats the process for all selected combinations of attribute values of all selected test functions.

Abstract: An auto-checking testing funtion generator is provided for generating auto-checking testing functions for procedures of a software interface from a formal specification specifying the procedures. The procedures are specified with procedure semantic expressions identifying the procedures and specifying their arguments, returning results, raisable exceptions, exceptional and normal terminations. Each exception or normal termination specifies the correct post-execution exception or normal termination state for the procedure given a particular pre-execution state. The procedure semantic expressions are boolean expressions constructed using comparison and boolean operators, calls to the procedure, auxiliary and special functions. The auxiliary functions are user supplied, and the special functions are supplied by the auto-checking testing funtion generator. An auto-checking testing funtion is generated for each procedure.

Abstract: A method and apparatus is disclosed for cooling a multi-chip module using embedded heat pipes. Semiconductor chips are disposed into the multi-chip module through cavities in the module substrate. The semiconductor chips engage heat pipes embedded within the substrate. The heat pipes conduct heat away from the semiconductor chips through a heat conductive bonding layer.

Abstract: A system and method is provided to perform quick patch level tests in a timely manner. The normal function of the patch is first computed using the convex hull property of the patch. The control points, which indicate the direction of the normals of the normal function, are used to construct a floating cone. This cone contains all the normals to the given patch. The floating cone is then moved in space and is truncated by two parallel planes orthogonal to the cone axis to contain the original given patch. From this information, frontfacing and backfacing volumes are constructed. These volumes are then used to derive information about the patch that can speed up its processing. For example, culling may be performed on the patch level before tessellation into triangles. The time consuming operations of computing normals and the floating cone are performed at the creation time of the patch and are view independent.

Abstract: In a computer system, a system boot prom having a bootstrap program is provided for booting the computer system from a boot device having a boot program and an operating system. The bootstrap program is designed to create a boot prom interface through which the boot program uses to locate the device driver for loading the operating system from the boot device. As a result, the device driver for the boot device may be provided in the system boot prom or a third party boot prom, thereby allowing the computer system to be booted from either a standard or a third party boot device without requiring rebuilding of the system boot prom.

Abstract: A high speed, low powered, BiCMOS TTL to CMOS translator circuit and method which relies on an internally generated reference voltage and which is capable of driving high loads. The translator circuit includes a first inverting and translating stage having a pull up transistor and a pull down transistor, a high gain stage and a second inverting stage.

Abstract: In a memory system having a main memory and a faster cache memory, a cache memory replacement scheme with a locking feature is provided. Locking bits associated with each line in the cache are supplied in the tag table. These locking bits are preferably set and reset by the application program/process executing and are utilized in conjunction with cache replacement bits by the cache controller to determine the lines in the cache to replace. The lock bits and replacement bits for a cache line are "ORed" to create a composite bit for the cache line. If the composite bit is set the cache line is not removed from the cache. When deadlock due to all composite bits being set will result, all replacement bits are cleared. One cache line is always maintained as non-lockable. The locking bits "lock" the line of data in the cache until such time when the process resets the lock bit.

Abstract: A cache array, a cache tag and comparator unit and a cache multiplexor are provided to a cache memory. Each cache operation performed against the cache array, read or write, takes only half a clock cycle. The cache tag and comparator unit comprises a cache tag array, a cache miss buffer and control logic. Each cache operation performed against the cache tag array, read or write, also takes only half a clock cycle. The cache miss buffer comprises cache miss descriptive information identifying the current state of a cache fill in progress. The control logic comprises a plurality of combinatorial logics for performing tag match operations. In addition to standard tag match operations, the control logic also conditionally tag matches an accessing address against an address tag stored in the cache miss buffer.

Abstract: The invention is an object-oriented graphic user interface for use in computer controlled display systems, and in particular, display systems having object oriented graphic interfaces. A central processing unit (CPU) is provided and is coupled to a display for displaying graphic and other data. The CPU is further coupled to a cursor control device which permits a user to selectively position a cursor at a desired location on the display, and signal the CPU of selections in accordance with the teachings of the present invention. Buttons are generated by the CPU and displayed which correspond to either a single function to be executed by the CPU, or a button stack which has associated therewith a plurality of functions disposed on a menu. The menu includes a plurality of buttons and/or button stacks. A button stack may be provided with a default function which is automatically executed by the CPU when a predetermined signal is provided by the user through the cursor control device.

Abstract: A method and apparatus for improving the testability of system logic of an integrated circuit having embedded memory arrays is disclosed. The embedded memory arrays are coupled to a binary constant generation and selection circuit which is also coupled to the system logic. During a test mode, the selection circuit sends a binary constant to the system logic in lieu of normal operational data output from the memory arrays. The system logic is tested while the binary constant is continuously applied.

Abstract: In a multiprocessor computer system, an access request and an access grant register is provided for storing an access request and an access grant semaphore for each shared resource. The access request and grant semaphores having a number of access request and grant bits assigned to the processors. Additionally, circuits are provided for each access request register for setting/clearing individual access request bits, and simultaneous reading of all access request bits of the stored access request semaphore. Furthermore, coordinated request and grant masks that reflect the relative access priorities of the processors are provided for the processors to use in conjunction with the current settings of the access request and grant semaphores to determine whether a shared resource is granted to a lower priority processor and whether a shared resource is being requested by a higher priority processor.

Abstract: A relocatable segment list builder, a system image dump driver, and a system image dump saver are provided to a dynamically configurable operating system being executed on a computer system. The operating system includes a root executable segment and a number of pageable relocatable segments that are loaded on an as needed basis. The relocatable segment list builder maintains in memory a non-pageable relocatable segment list, which comprises names of the relocatable segments that are loaded in any particular point in time. The system image dump driver dumps an image of the operating system including the non-pageable relocatable segment list to a dump device at the time of a system crash. In addition, a system image saver is provided to the computer system. The system image saver builds a system image dump file, which comprises the relocatable segment list dumped using the operating system image dumped.

Abstract: An apparatus and method for converting a non-English language document text or search and retrieval argument into a form which can be processed by an existing ASCII based automated text processing system, even though the non-English language may have thousands of characters in it, thereby allowing the use of existing text processing systems and existing text data bases without the need to convert these text processing systems to handle multi-byte character languages.

Abstract: In a computer system having a frame buffer, apparatus for providing an overlay for the frame buffer, and a digital-to-analog converter for furnishing analog signals from the frame buffer to a pedestal setup display monitor, the digital-to-analog converter including apparatus for furnishing a blank level substantially below the lowest level of the analog signal desired to be visible on the monitor during retrace periods when used with a pedestal setup display monitor, the improvement including apparatus for allowing the system to utilize zero setup display monitors including apparatus for disabling the apparatus for furnishing a blank level when the computer system is used with a zero setup display monitor, and apparatus for causing the apparatus for providing an overlay for the frame buffer to furnish signals indicating a black level during retrace periods when the computer system is used with a zero setup display monitor.

Abstract: A method and apparatus for scoped interprocess message switching between a sender process and a plurality of receiver processes is disclosed. Messages supported may be scoped to message scopes of a message scope type of "Session" or one of a plurality of non-session message scope types including a message scope type of "File". Messages may also be scoped to message scopes of an intersection or union of message scope types. Intersection and union of message scope types comprise "File in Session" and "File or Session". Scoped messages supported further comprise request and notice messages. Receiver processes supported comprise handler processes and observer processes. Request messages may be observed as well as handled, and notice messages may be handled as well as observed. Handler and observer processes may be non-executing as well as executing. Local receiver processes are selected for session scoped messages. Remote as well as local receiver processes are selected for non-session scoped messages.

Abstract: An integral heat pipe, heat exchanger, and clamping plate. A base plate functioning as an evaporator has disposed in it a multiplicity of intersecting parallel and perpendicular internal channels extending laterally substantially across the base plate. A sintered copper thermal wick is applied to all channels. Thin-walled condenser tubes forming a condenser region are joined to the base plate at intersections of width wise and cross wise channels contained in the base plate. A multiplicity of fins extend to all condenser tubes. For heat pipe arrangements operating in horizontal configurations, all wick-lined channels within the base plate remain open. For heat pipe arrangements intended to operate in oblique or vertical configurations, horizontally extending channels vertically displaced relative to other horizontal channels are isolated from the latter by a multiplicity of plugs.

Abstract: A method and apparatus for selecting an entry to be replaced in a translation lookaside buffer in a computer system. The translation lookaside buffer stores a plurality of entries of virtual-to-physical address translations with each entry having a used bit and a valid bit.

Abstract: The method and apparatus provides a parity bit for every m multiples of b bits, a group of b bits being the smallest number of bits that can be manipulated by the CPU. The parity bit is computed for the entire m x b bits during a write operation, even if only a subset of the m multiples of b bits is being stored. The write operation is implemented as a read-modify-write operation of the entire m x b bits, with parity error reporting suppressed for the read portion of the operation. However, the parity bit is set factoring in whether a parity error is detected during the read portion of the operation. The parity bit for the entire m x b bits is checked during a read operation, even if only a subset of the m multiples of b bits is needed. Any detected parity error is reported to the CPU. As a result, hardware cost is substantially reduced with minimal degradation to data integrity. Furthermore, the method and apparatus is completely transparent to the CPU and the operating system.