Abstract: A digital data processing system employs a single-chip microcomputer device having separate on-chip program and data memory, executing instructions in a single machine state. An external program address bus allows off-chip program fetch in a memory expansion mode, with the opcode returned by an external data bus, or all program storage can be off-chip in a system emulator mode. The ALU and accumulator have 32-bit data paths, while the busses are 16-bit. Various test modes are permitted; for example, the internal program ROM may be read out on the data bus, one opcode at a time, for test purposes without executing the opcodes.

Abstract: The randomly-generated energy produced by decay of a radioactive source is utilized to generate timing signals for horologic and chronographic instruments such as electronic watches, clocks or chronometers. The radioactive source is implanted by ion implantation or diffusion in or near the depletion region of a P-N junction semiconductor device which may be integrated on a common semiconductor substrate with the electronic timekeeping circuitry of the horologic or chronographic instruments. Individual pulses due to beta radiation produced in the depletion region causes electron migration from the P to the N region of the device and produces electrical pulses. These pulses are amplified and counted until a preselected count is reached. When such count is reached, the timekeeping circuitry is stepped by one second or some convenient fraction thereof.

Abstract: The removal of residual impurities from semiconductor material is accomplished by solid state electromigration of the impurities from the semiconductor slice into a surrounding conductive liquid (e.g. Hg) which is maintained at a negative potential.

Abstract: One embodiment of the present invention provides a method whereby a symmetrical transistor may be fabricated which eliminates the problems of scalability caused by the requirement of fabricating an extrinsic base. The method accomplishes this by the use of a polysilicon extrinsic base structure which is formed in a trench containing an insulating layer in the bottom of the trench formed by differential oxidation.After fabricating appropriate isolation structures, two trenches for either side of the intrinsic base are cut into the surface of the substrate. The bottom of these trenches are then heavily doped. A silicon dioxide layer is then thermally grown in the trenches. Because the bottoms of the trenches are heavily doped, a thicker silicon dioxide layer is formed in the bottom of the trenches. This silicon dioxide layer is then etched so that the silicon dioxide layer is completely removed from the sides of the trench but remains in the bottoms of the trench.

Abstract: A plasma etch process for etching titanium nitride selectively with respect to titanium silicides. A reducing electrode, a low flow rate, and a non-copious fluorine source (such as CF.sub.4) are used to achieve a fluorine-deficient plasma. Preferably the substrate temperature is allowed to rise above 50 C during etching.

Abstract: In manufacture of VLSI semiconductor devices, the insulator surface upon which a metallization pattern is deposited is made more smooth by the deposition of a thin insulator in liquid form. This insulator may be silicon oxide deposited from a solution, or otherwise from a liquid carrier, spun on to create thick portions in corners and steep edges, thus promoting improved step coverage. The insulator may be phosphorous-doped so the subsequently-applied thick oxide may be undoped, permitting a two-step wet/dry etch for contact holes, producing sloping sides to reduce metal thinning.

Abstract: DRAM cells and arrays of cells on a semiconductor substrate, together with methods of fabrication, are disclosed wherein the cells are formed in pairs or quartets by excavating a trench or two trenches through the cell elements to split an original cell into two or four cells during the fabrication. The cells include vertical field effect transistors and capacitors along the trench sidewalls with word lines and bit lines crossing over the cells.

Abstract: A starter circuit for a fluorescent tube lamp is connected between the cathode heaters of the tube to provide an initial heating current and then changes to a high impedance to ignite the tube. The circuit is fed by raw rectified a.c. and has a main thyristor requiring a high holding current to maintain the initial conduction. The current through the main thyristor sets up a voltage across a series diode which triggers a second thyristor to reduce the gate voltage of the main thyristor. The main thyristor ceases conduction when the current falls below the holding value and the inductive ballast impedance then produces a high energy striking pulse for the tube. The pulse voltage is limited to increase its duration. One embodiment generates a single pulse only each time the circuit is switched on and another embodiment produces pulses for a period of time before becoming quiescent. The main thyristor and the voltage limiting means are embodied in a monolithic semiconductor structure.

Abstract: A CCD imager of small geometry which has increased well capacity. An additional p-type implant 112 selectively located creates a p-type region 112 below the channel region 13 of the virtual well regions 34, which increases the capacitance in the virtual well regions 34.

Abstract: The present invention discloses a method for planarizing contact holes, vias, and other surface depressions, during the fabrication of an integrated circuit structure. Differential thermal conductivities are exploited to selectively remove a deposited film of metal from high-thermal-resistance areas, such as silicon dioxide or other insulators, and not from low-thermal-resistance areas, such as silicon or metal. By repetition of this step, very deep depressions, having a high aspect ratio, are reliably filled.

Abstract: A token ring access control protocol circuit which includes an M/T converter for converting incoming serial data in differential Manchester encoded form into transitional encoded form. Next the data is fed into a shift register and held temporarily while it is compared with preset sequences to determine if it is a starting delimiter or an ending delimiter. If a starting delimiter pulse is generated and used to synchronize subsequent circuitry if required. Data from the shift register is continuously sampled with at least a 2 baud delay by a data sample latch circuit which provides and output line for data values and another output line for code violation signals. The data values and code violation values go to a data receiving circuit which processes the data, and loads it onto a local data bus for transmission to other parts of a token ring control system.

Abstract: Two-terminal active devices, such as IMPATT and Gunn diodes, are combined with passive devices in a monolithic form using a plated metal heat sink to support the active elements and a coated-on dielectric to support the passive elements. Impedance-matching circuitry is preferably placed very close to (or partially overlapping) the active device, thereby eliminating detrimental device-to-circuit transition losses.

Abstract: An improved surface mounted system for leaded semiconductor devices has J-shaped device leads soldered to respective portions of circuit pads on a printed circuit board, each lead having inner and outer surfaces of the J-shape covered with solder dewetting and solder wetting metals respectively which are metallurgically bonded to a metal core of the lead formed of a springy, relatively high electrical conductivity metal.

Abstract: A computer system extracts horizons, each defined by a network of points in a first format from within a three-dimensional volume. Each point is tagged with a plurality of parameters including links in the X and Y direction for interconnecting the points. The system accesses any one of the points in the network then accesses every point that is linked directly or indirectly to the first accessed point. An address pointer is established for each of the accessed points, to define a second format. A second format is in a two-dimensional array and any point that is accessed a second time is rejected to prevent any spiraling of the horizon. The second format may be stored and displayed.

Abstract: A FLIR imager is modified to include a hybrid optical/electronic processor for automatic local area dynamic range normalization. FLIR imagers have an objective lens for focusing IR energy emanating from a scene on a detector array. The detector array generates electrical signals representative of the scene. LEDs generate a visible picture of the thermal image of the scene for a video processor for formatting the signals for a particular type display (TV). The hybrid optical/electronic processor is inserted between the LEDs and the video processor; it includes a beamsplitter for directing the image to a pair of CCD cameras. The image at one camera is set in sharp focus to preserve all of the spatial frequency content (allpass) through the image reconstruction optics. While the image at the second camera is slightly defocused for averaging image information over small local regions the size of the defocused point spread function (spatial lowpass filtered).

Abstract: A pressure sensor probe has a first port connectable to a relatively low pressure source in a compressor crankcase and a second port connectable to a relatively high pressure source at the output of an oil pump. A shuttle is slidably disposed in a bore and has a first end which closes the first port when the difference in pressure between the two ports indicative of normal operation exceeds a selected value determined by the relative areas of the shuttle exposed to the respective pressures and by a coil spring which biases the shuttle away from the first port. A passage is formed between the shuttle and the bore leading from the second port to a force receiving surface on the high pressure side of the shuttle. The length and cross sectional area of the passage is selected to provide a desired dampening or time delay between the high pressure source and the force receiving surface. A control circuit includes a reed switch whose state of actuation is dependent upon the position of the shuttle.

Abstract: Vertical AlGaAs heterojunction bipolar transistors (30) with planar structure together with fabrication methods therefor are disclosed. For an emitter (44) on top structure, the contacts (46) to the base (38) are formed by a diffusion of zinc dopants from the surface, and contacts (42) to the collector (34, 36) are formed by diffusions of sulfur dopants from the surface rather than by etch of connecting vias. Further, device isolation is also provided by zinc diffusions (54) rather than by mesa formation. These diffusions are by rapid thermal pulses.

Abstract: A metal gate and contact/interconnect system for MOS VLSI devices employs a multiple-level refractory metal structure including a thin layer of molybdenum for adhesion to oxide and a thicker layer of tungsten over the molybdenum. The metal gate is encapsulated in oxide during a self-aligned siliciding operation. A contact to the silicide-clad source/drain region includes a thin tungsten layer, then the molybdenum/tungstem stack, and a top layer of gold.

Abstract: A semiconductor integrated circuit, such as a high-density, dynamic read/write memory containing an array of rows and columns of memory cells, is constructed to allow high speed testing to identify row line faults in one example, and to identify column or sense amplifier faults in another example. Row lines for the array in a dynamic RAM may contain detector circuits activated in a special test mode to produce a data output indicating integrity of each row line without requiring the access of the cells in the array in complex data patterns. The connection between bit lines in the array and sense amplifiers may be shifted or transposed in another embodiment to distinguish between column or sense amplifier faults; this construction also allows rapid loading of test patterns.

Abstract: The present invention relates to construction of nonsymmetrical N bit parallel data processing circuits using a plurality of identical integrated circuits chips. In such nonsymmetrical structures it is often impossible to provide a design employing identical integrated circuit chips using conventional techniques. The structure is first divided into single bit slices. These single bit slices are then examined to determine the number of each differing single bit type. A common divisor M is sought for the entire set of B(I)'s, where B(I) is the number of bits of the I-th type. A partial structure is formed in which B(I)/M of each I-th bit type is provided. The number M identical integrated circuits of this partial structure are formed. Lastly, these identical integrated circuits are interconnected to form the whole structure desired.