Abstract: A method of forming a lateral bipolar transistor in a semiconductor substrate of a second conductivity type by an MOS or CMOS process which includes growing a thin insulating layer over the substrate and diffusing a tank region of a first type of conductivity into the semiconductor substrate of a polarity opposite to that of the second conductivity type. A strip of polysilicon is deposited around a region between the emitter area and collector area on a face of the substrate over said oxide. Next an emitter region having the form of a band enclosing an undiffused central region within the polysilicon strip and a collector region located outside of the strip are diffused into the tank. The polysilicon prevents diffusion of implanted impurity into the tank region over which is superimposed the polysilicon. An electrically conducting layer is formed over the emitter and a portion of the polysilicon.

Abstract: A vibrator seismic source has a sweep generator for providing a pilot signal and sensors for generating a feedback signal representative of the force imparted to the ground by the vibrator pad. Circuitry is incorporated for separating the fundamental signal from the feedback signal and for separating the distortion from the feedback signal. Means are provided for generating a control signal for controlling the action of the vibrator means. Included are means for reducing the amplitude of the pilot signal a designated amount, determined by the distortion, and means for algebraically summing the reduced amplitude pilot signal and the fundamental signal to provide an error signal. The error signal is input to a loop filter to perform real time correction of the control signal. The reduced amplitude pilot signal is input to means for adjusting the control signal for trends in the distortion.

Abstract: A CCD imager wherein a mixed MOSFET and JFET periphery is provided using the same device doping profiles as are used for fabrication of the CCD structure. This provides simple fabrication of low-noise amplifiers integrated with the CCD array. Preferably the gate of the JFET is formed with the same implant which forms the virtual phase electrode in an array of virtual phase CCD cells. Preferably the JFETs are used as loads in source-follower stages. Preferably the MOSFET devices include both buried-channel and surface-channel devices connected to a common drain voltage; the buried-channel devices are used for earlier stages of amplification, where they can be operated in their low-noise regime, and the surface channel used for output stages. If buried channel devices were used for the output stage, then the buried-channel devices in the prior stage would have to be biased into a high-noise regime to achieve the necessary output voltage swings.

Abstract: An improved voice messaging system using LPC baseband speech coding. In standard LPC-based baseband speech coding techniques, LPC parameters plus a residual signal are transmitted. To save band width, the residual signal is filtered so that only a fraction of its full bandwidth (e.g., the bottom 1 KHz) is transmitted. At the decoding station, this fraction of the residual signal (which is known as the baseband signal) is copied up or otherwise expanded to higher frequencies, to provide the excitation signal which is filtered according to the LPC parameters to provide the reconstituted speech output. However, this tends to produce perceptually significant ringing effects and high frequency distortion in the reconstituted signal. The present invention uses a variable baseband width, which is adaptively varied, in accordance with an integral multiple of the frequency of the pitch of the input signal, to provide a more appropriate harmonic match in the reconstituted excitation signal.

Abstract: A logic circuit that has a plurality of stages that are driven by a clock source that provides at least 2 clock signals and includes at least a single latch stage located between two of the plurality of stages is configured with field effect transistor technology. The latch stage includes an isolation means for isolating the preceding circuit of the plurality of stages from flow-through of the clocks and signals that are connected to the latch stage, and a latch circuit for storing the data that is applied to the latch stage between clock pulses. A plurality of latch stages can easily be configured as a shift register latch.

Abstract: A signal peaking device for a single line video input has a transversal filter with a plurality of sample and hold (S & H) circuits, a corresponding plurality of line drivers and output switches. The output switches are connected to a plurality of weighting circuits and a summer that sums the weighted output of the output switches. A free running digital shift register generates the sample pulse that operates the sample and hold circuits.

Abstract: A dual function sensor particularly useful with vehicular coolant systems indicates when a coolant liquid becomes corrosive to such cooling system materials as well as when the liquid falls to a low level condition. A reference and a sense electrode are used to probe the condition of the coolant liquid. Integral electronics provide signal conditioning and transmitting to indicate both corrosive and low level coolant conditions. The sensor assembly mounts directly onto a tubular coupling on the vehicle radiator by pushing the assembly onto the coupling until a spring wire element snaps past a lip formed on the free distal end of the coupling. An electrical connector shroud extends from the assembly and accommodates a mating male connector which is pushed onto the shroud until a clip mounted on the male connector snaps over a locking tab located on the shroud. The male connector typically is connected to an engine control module (ECM).

Abstract: A semiconductor memory comprises four arrays (10), (12), (14) and (16) disposed on a single semiconductor chip. Each of the arrays has a serial shift register (86) associated therewith. Data is transferred from the bit lines of the associated array through a transfer gate (90) for storage in the shift register (86). A tap latch (88) is provided on the output of each of the shift bits in the shift register (86) for determining the output therefrom. The tap latch (88) stores a tap decode signal which is decoded from a tap address by the column decoder (30). The column decoder (30) also decodes the column address in the random mode. The tap decode signal selects any of the shift bits in the shift register (86).

Abstract: A voltage comparator for an analog to digital converter is provided which includes several differential amplifier stages connected in cascade that determine the existence of a voltage difference between the two input signals and amplify this voltage difference successively. The comparator further includes offset correction voltage circuits which are connected to each differential amplifier stage and allow for the correction of errors caused by the mismatching of the devices internal to each of the differntial amplifier stages.

Abstract: A video memory and display (CRT) controller circuit on a single semiconductor substrate controls a DRAM (dynamic random access memory) used as a video memory and a CRT display. The video memory and display controller is normally a part of a video system which includes a data processor, video memory and a CRT display. The video memory and display controller includes a row address latch for storing a row address, a column address latch for storing a column address, display address logic which generates row and column addresses for display update ad refresh logic which generates row addresses for the required periodic DRAM refresh. A multiplexer provides the application of the proper address to the address bus of the DRAM. The display controller circuit is responsive to the data processor data bus for generating display control signals for control of the CRT display.

Abstract: A High Speed Multiplier/Divider for use with high speed processors that have dedicated adders, registers, controls and logic for performing a multiply operation, a multiply and add operation, and a divide operation. The multiply/divide circuit has capability of multiplying a 16 bit word times a 16 bit word that produces a 32 bit product with divide being the inversed of the multiplication operation and may use signed or unsigned multiply/divide. A Booth algorithm is used to implement the multiply operation and the multiply/divide operations are operating asynchronous, that is, at the completion of one set of operations, the next set is implemented.

Abstract: A memory apparatus including an array of storage elements connected to a plurality of addressing lines for selectively connecting a group of the storage elements to a plurality of data lines. Protection circuitry is provided that is connected to the address lines for storing flags corresponding to selected groups of the storage elements to be protected. Write circuitry is provided that is connected to the address lines and to the array of storage elements for preventing the writing into the storage elements addressed by the address lines when the address is within the address of the protected groups. Control circuitry is provided that is connected to the protect circuit and the write circuit for controlling the input of the protect group addresses and for enabling the write circuit means during a write operation. The memory apparatus further includes the capability to provide protection from writing from a direct memory access source or from a central processing unit source.

Abstract: A semiconductor device is programmed by a laser beam which causes an electrical short between two conductors on a silicon substrate, as by melting an insulator between the conductors and fusing or shorting the conductors. The conductors may be first and second levels of polycrystalline silicon in a standard double-level poly process, and the insulator is thermal silicon oxide. The laser beam is focused on an area which is shielded from the silicon substrate by the first-level conductor, so heating and disruption of the substrate or underlying circuit structure is minimized.

Abstract: Delayed release locking control device, particularly for doors of washing machines and the like, containing inside a case a self-regulating resistive wafer heater of a material having a positive temperature coefficient (PTC) of resistance, a snap-acting bimetallic element connected to a latch or locking member, and terminals which carry electrical current to the PTC wafer heater, wherein the bimetallic element is arranged so means transform the linear snap like movement of an end of the bimetallic element into a rotary movement of the latch mounted on the case to cause it to rotate 90.degree. from a resting position into an operating position when the bimetallic element, selectively heated by the said PTC wafer, abruptly reverses its curvature upon reaching the actuating temperature of reversal and to cause the said latch to return to the resting position when the bimetallic element cools down again to below a reset temperature of reversal and snaps back to its normal curvature.

Abstract: The disclosure relates to the chip organization and circuit arrangement of a gallium arsenide MESFET memory for high speed, low power and radiation hard application. The memory is organized into several columns, each column having several memory cells and a sense amplifier. The write and read/sense data buses are placed at the input and output of the sense amplifier to provide better impedance matching to the write and read/sense circuits. The memory circuit as well as the output circuit utilize a combination of d-mode and e-mode gallium arsenide transistors in judicious arrangement to obtain low power requirements and reduced chip size relative to prior art gallium arsenide systems providing the same function and having the same general read access time.

Abstract: The disclosure relates to a three dimensional semiconductor structure formed in a semiconductor substrate wherein electrical components, both active and passive, are formed on the substrate surface as well as in grooves formed in the substrate at an angle and extending to the surface. The substrate surface is designed to lie in a predetermined crystallographic plane of the substrate material and the grooves extend in a predetermined crystallographic direction from said plane, this being accomplished by orientation dependent etching.

Abstract: In a video computer system, an improved memory circuit is provided which is effective for delivering stored data only at appropriate instances, and which is also simpler and more reliable in design. In particular, the system preferably includes a bit-mapped RAM circuit which assumes a serial mode in response to both a row address signal and a suitable data output control signal, and which assumes a parallel or "random" mode when only the row address is received. Stored data is transferred to a parallel output terminal in the RAM circuit, or to a serial output terminal therein, depending upon the sequence of these signals as well as the column address and read signals, whereby the data output control signal is used for two separate and different purposes within the system.

Abstract: An electrostatically deflectable beam spatial light modulator with the beam composed of two layers of aluminum alloy and the hinge connecting the beam to the remainder of the alloy formed in only one of the two layers; this provides a thick stiff beam and a thin compliant hinge. The alloy is on a spacer made of photoresist which in turn is on a semiconductor substrate. The substrate contains addressing circuitry in a preferred embodiment.

Abstract: A dual function sensor particularly useful with vehicular coolant systems indicates when a coolant liquid becomes corrosive to such cooling system materials as well as when the liquid falls to a low level condition. A reference and a sense electrode are used to probe the condition of the coolant liquid. Integral electronics provide signal conditioning and transmitting to indicate both corrosive and low level coolant conditions. The sensor assembly mounts directly onto a tubular coupling on the vehicle radiator by pushing the assembly onto the coupling until a spring wire element snaps past a lip formed on the free distal end of the coupling. An electrical connector shroud extends from the assembly and accommodates a mating male connector which is pushed onto the shroud until a clip mounted on the male connector snaps over a locking tab located on the shroud. The male connector typically is connected to an engine control module (ECM).

Abstract: A process is disclosed for fabricating N-wells in a P-type substrate. An N-type epitaxial layer is formed on the surface of a P+ substrate. The N-type epitaxial layer is then masked and a doubly charged boron implant is performed on the exposed areas of the N-type epitaxial layer. Because of the lower mass of boron, a common production 200 kiloelectron volt implanter provides sufficient implantation energy to doubly charged boron to provide a P region which extends through the N-type epitaxial layer. The remaining N-type portions of the epitaxial layer provide N-wells for the fabrication of complementary field effect transistor circuitry.