Abstract: A housing has a switch chamber in which an electric switch is placed and a recess in which is received a snap acting, thermally responsive disc which actuates and deactuates the switch upon snapping from one configuration to another. A drop in thermal biasing assembly used to modify the operating temperature of the disc has a pair of cylindrical film type resistors electrically connected in parallel circuit relation and physically connected to a pair of connectors. An assembly having resistors of a rating chosen for a particular application is dropped into the recess before the disc is assembled, the connectors sliding into matching bores formed in the housing. The connectors are attached to suitable teminals and the disc is then placed over the thermal biasing assembly to provide a multiple temperature operating thermostat.

Abstract: The present invention relates to a video display controller system which permits a variety of differing video attributes for each displayed character. A character code is stored in a character memory and an attribute code is stored in an attribute memory at corresponding memory locations for each display position. In accordance with the present invention the transfer of data to and from the attribute memory is through an attribute latch. Each time a character is written into the character memory the attribute stored in the attribute latch is stored in the corresponding location in the attribute memory. Similarly, the attribute stored in the corresponding location of the attribute memory is stored in the attribute latch upon reading a character from the character memory. The attribute latch can be independently read out or written into. This technique is advantageous for specifying a display screen in which many characters have the same video attribute and for executing block moves within the display screen.

Abstract: A two-lead Hall effect sensor (10) has a combined voltage supply and output terminal (12) and a ground or reference terminal (14). A Hall device (16), a comparator (18) and a voltage/current converter (20) are each connected between terminals (12) and (14). Hall device (16) supplies a first signal to comparator (18) when it senses a magnetic field strength above a predetermined amount, and supplies a second signal in the absence of the magnetic field strength. Comparator (18) in turn supplies either a first voltage state or a second voltage state to the converter (20). Converter (20) converts the first voltage state into a first current appearing at terminal (12), indicating the sensing of a magnetic field, and similarly converts the second voltage state to a second current, indicating a weak or absent magnetic field.

Abstract: An improved circuit panel connector comprises an electrically insulating body having a plurality of openings extending through the body and has electrical contacts such as screw machine contact assemblies movably mounted in the respective body openings so that posts extend from the openings at one side of the body and terminal entry portions of the contacts are accessible at an opposite side of the body. A plate having a plurality of protuberances formed therein is disposed over the opposite connector body side with the protuberances fitted into the terminal entry portions of the contacts for spacing the movably mounted contacts relative to each other in the connector body openings. A polyimide tape is adhesively and detachably secured to the body over the plate for holding the plate on the body and for sealing the body openings. The contact posts are inserted into corresponding openings in a circuit panel and soldered to circuit paths on the panel.

Abstract: A digital multiplication circuit for a microprocessor utilizes a modified Booth algorithm for implementing the digital multiplication of two numbers and includes a Booth recoder for recoding the multiplier into a selected number, n, of Booth operation sets where n is a positive integer that equals one-half the number of bits in the multiplier. Each operation set is applied to a second plurality of n partial products selectors which are connected in cascade arrangement according to multiplicand sets and wherein each partial product selector multiplicand set implements one of the recoded Booth operation sets. The outputs of the partial product selectors are summed by a summation means and a domino circuit means provides an evaluation pulse for each member of the partial product selector at the completion of the Booth operation set that is connected to the partial product selector.

Abstract: The method includes generating a binary signal (S4A to S4D) which is time modulated. To do this, an alternating signal (S1) is compared with a known cyclical signal (S5) and a threshold signal. There is measured the durations between the transitions of the modulated signal by means of a high speed clock and by means of counting in the positive and negative directions of the clock pulses for one or more periods of the signal under examination. If, after counting, a residual value is found, one generates a binary signal representing the transition.

Abstract: The present invention relates to a self testing data processing system which includes a communications bus enabling communication between nonintelligent data processing circuits and a plurality of intelligent data processing circuits. The communications bus has connection slots, each connection slot having a unique electrically readable slot number. Each data processing circuit connects to the communications bus via one of the connection slots. Each data processing circuit has an identity memory which indicates whether or not that circuit can be a system test master. In addition, all intelligent data processing circuits include within their identity memory an indication of whether or not they have passed a circuit self test. Upon initial application of electric power or upon system reset, each intelligent data processing circuit performs a circuit self test and then sets the identity memory to indicate whether or not they have passed this self test.

Abstract: A single-ended, bandpass, two stage monolithic (integrated) medium power amplifier is disclosed. The first stage of the amplifier includes a field effect transistor (FET) amplifier having a gate width of about 900 microns and the second stage a "split" field effect transistor (FET), i.e. two parallel connected FETs having gate widths of about 600 microns. The amplifiers of both stages have symmetrical biasing circuits providing the option of biasing the power amplifier from either side of the chip. The "split" (1200 micron) FET of the second stage decreases source inductance and reduces the thermal impedance.

Abstract: A microprocessor device used as an adapter for a communications loop of the closed-ring, token-passing, local area network type. Each station on the ring has a host processor with a host CPU, a main memory, and a system bus. The microprocessor device, operating relatively independent of the host CPU, is coupled to the main memory by the system bus and includes a local CPU, a local read/write memory, an on-chip timer, a local bus and a bus arbiter. A transmit/receive controller is connected between the ring and the microprocessor device. This controller is coupled to the local bus to directly access the local read/write memory, also under control of the bus arbiter. The local CPU executes instructions fetched from a ROM accessed by the local bus, so the local CPU instruction fetch, the direct memory access from the transmit/receive controller for transmitting or receiving data frames, and the access from the host CPU for copying transmitted or received message frames, all contend for the local bus.

Abstract: A motor protector of the type having a snap acting thermostatic element is shown particularly adapted for use with compressor motors in which a conventional three pin header is mounted on the compressor casing to allow electrical energization of the motor. An improved heat transfer path is formed between the windings of the motor and the thermostatic element of the protector by suspending the protector from one of the motor pins in optimum heat conductive relation therewith and thermally separated from the compressor casing and any component mounted on the other two pins.

Abstract: A cylinder pressure transmitter has a body with a chamber open at one end accommodating pressure responsive piezoelectric means. A cup-shaped diaphragm member has a side wall secured with a laser weld to a neck portion of the body which is formed as a rim around the chamber opening. The bottom of the member extends over the opening and has a slightly domed portion exposed to the pressure in a cylinder of an internal combustion engine to serve as a diaphragm responsive to variations in cylinder pressure to apply corresponding pressure forces to the piezoelectric means, thereby to provide initial electrical signals corresponding to the cylinder pressures. Electronic means are carried on the body to amplify the initial electrical signals for transmission to computer control means at a location remote from the cylinder for regulating engine operation to improve performance.

Abstract: A read only memory device with a matrix of series connected FET's addressed with X and Y decoding, a control switch between the output line and a voltage source operant to connect or not the voltage source to the output line in response to a control signal phi, and a second control switch, responsive to the same signal phi, provided between ground and each string of series connected FET's.

Abstract: A charge transfer device (CTD)/complementary metal oxide semiconductor (CMOS) process for the production of a signal processing apparatus is disclosed. The process consists of selectively combining virtual phase CCD process technology with CMOS technology to provide high density signal processing utilizing small (3 micron) geometries, sized P and N MOS (CMOS) transistors, and high valued (0.8 picofarad) poly-poly capacitors. The process is a single and efficient (14-16 photomasks) fabrication process starting with a single layer of P+ silicon as a substrate supporting an epitaxial layer of P silicon as the active area. An N well is formed in the epitaxial surface for a P-channel MOSFET, then using a patterned moat and positive and negative resists boron is ion implanted to form channel separators between N and P channel transistors, and P+ isolation regions and channel stops for the CCDs.

Abstract: An enclosed, electronic system has a plurality of lower power-dissipating electronic components mounted on a chassis. The components are positioned adjacent each other to form low volume fluid ducts therebetween. A low volume fluid duct is formed between one side of the plurality and one end enclosure of the system. At least one higher power-dissipating electronc component is also mounted on the chassis, forming a high volume fluid duct between one of its sides and one side of the last of the lower power-dissipating electronic components, and a high volume fluid duct also formed between the other side of the higher power-dissipating electronic component and the other end enclosure. Air is caused to blow through the low volume fluid duct and then to be exhausted through the high volume fluid ducts. The rate of air flow through the high volume ducts is one half of the minimum required to cool the higher power-dissipating component.

Abstract: Molybdenum-gate transistors with self-aligned, silicided source/drain regions are made by a process that avoids unwanted etching of the molybdenum of the gate when the unreacted metal used for siliciding is removed. The molybdenum gate is protected by encapsulating with a cap oxide and sidewall oxide; this encapsulation is applied in a manner to seal the interfaces between the two oxides. The oxides may be dual layer--first plasma deposited then phosphorus doped CVD oxide. A dilute sulphuric acid etch may be used to remove unreacted titanium employed for the siliciding.

Abstract: Proven data base is generated for electrical test responses of sporadic defects in integrated circuits as manufactured. Manufactured circuits are subjected to that electrical testing and resulting responses used to identify defect and check the manufacture to avoid its repetition.

Abstract: A microwave varactor network wherein parametric oscillation modes are suppressed by coupling the varactor, with very low intervening impedence, to a bias regulator circuit (preferably an emitter follower circuit) through which the varactor bias voltage is supplied. The emitter follower is biased to always be carrying current, which improves its response time in compensating any transient bias voltage variations which appear across the varactor.

Abstract: A sensor (10) responding to the action a force comprises a base body (12) and a force takeup element (14) which is connected to the base body (12) via at least one support element (16, 18, 20, 22). The support element deforms under the influence of a force acting on the takeup element (14). In the deformation region between each support element (16, 18, 20, 22) and the force takeup element (14) a measuring member (32, 34, 36, 38) is disposed which reacts to the deformation with a change in a physical parameter. An uninterrupted conductor path (44) is provided which extends from a first terminal land (46) on the base body (12) via each support element (16, 18, 20, 22) and the force takeup element (14) to a second terminal land (48) on the base body (12).

Abstract: A microprocessor device is used in an adapter for a communications loop of the closed ring, one-way, token-passing local area network type. Each station has a host processor with a host CPU, a main memory, and a system bus, and has an adapter including the microprocessor tested according to the invention. The adapter coupled to the main memory by the system bus and includes a local CPU (the microprocessor), a local read/write memory, and a local bus. A transmit-and-receive controller is coupled to the local bus to directly access the local read/write memory; when this station receives a free token, the transmit-and-receive controller copies the message frame to be transmitted from the local read/write memory to the outgoing signal path, converting from parallel to serial. When a message addressed to this station is received, the controller converts it from serial to parallel, and copies the message frame into the local read/write memory via the local bus.

Abstract: One embodiment of the present invention provides a polycrystalline silicon loading device occupying a minimum of surface area in an integrated circuit. A very thin layer of silicon nitride is formed on the surface of a heavily doped contact point in the integrated circuit. An undoped layer of polycrystalline silicon is then formed on the surface of this thin layer of silicon nitride. A thin layer of silicon nitride is then formed on the surface of the undoped polycrystalline silicon layer. Finally a heavily doped polycrystalline silicon layer for making contact to the loading device is formed on the surface of the second thin silicon nitride layer. Because the two thin silicon nitride layers are very thin, tunneling current through the silicon nitride layers begins at a fairly low threshold level. After tunneling occurs, the main resistance element of the load device is the undoped polycrystalline silicon.