Abstract: A semiconductor read/write memory device has a normal mode of operation and a test mode. The test mode allows concurrent writing to a number of cells in the cell array so that test patterns may be rapidly loaded. The cell array is split into subarrays and the column addressing circuitry is arranged to provide a maximum of spacing between the cells that are concurrently written. In this manner, pattern sensitivity tests may be run at higher speed because a number of bits at widely spaced positions in the array can be tested simultaneously.

Abstract: A portable educational device that is adapted to be used in conjunction with a counter (12) having a display (14) and a keyboard (16) for input of data. A memory slot (18) or an alternate port (19) is provided on the computer (12) to receive the educational device (20). Educational device (20) contains a keypad (24) and a display (26) and operates independent of the computer (12). The educational device (20) includes a central processing unit (48), a Read Only Memory (42) and a Random Access Memory (44). A primary power source (54) supplies power to the educational device (20) during the operation thereof. A back-up power source (56) provides power to the Random Access Memory (44) to form a non-volatile memory for retention of data during periods of non-use. A connector (34) interfaces with the computer (12) to allow the computer (12) to address the Random Access Memory (44) to retrieve data stored therein and to store data at selected locations therein for use by the Central Processing Unit.

Abstract: A radar rotary joint usable at all frequencies, but particularly useful at millimeter wavelengths includes an inner housing, an outer housing, bearings for rotatably interconnecting the inner and outer housing, and irises for converting the mode of incoming and exiting electromagnetic energy. The inner housing has a TE.sub.11 mode circular waveguide, a TM.sub.01 mode circular waveguide and a right angle transition for converting the TE.sub.11 mode to TM.sub.01 mode and an outer surface forming a bearing support, an outer bearing housing for enclosing the bearings and bearing retainers for retaining the bearings between the outer bearing housing and the bearing supporting surface of the inner housing. The outer housing is attached to the outer bearing housing and includes a TM.sub.01 mode circular waveguide, a TE.sub.11 mode circular waveguide and a right angle transition for converting the TM.sub.01 mode to the TE.sub.11 mode. An inline junction input iris attached between a TE.sub.

Abstract: A semiconductor integrated circuit, such as a high-density, dynamic read/write memory containing an array of rows and columns of memory cells, is constructed to allow high speed testing to identify row line faults in one example, and to identify column or sense amplifier faults in another example. Row lines for the array in a dynamic RAM may contain detector circuits activated in a special test mode to produce a data output indicating integrity of each row line without requiring the access of the cells in the array in complex data patterns. The connection between bit lines in the array and sense amplifiers may be shifted or transposed in another embodiment to distinguish between column or sense amplifier faults; this construction also allows rapid loading of test patterns.

Abstract: A vibrator seismic source has a hydraulic system, including a pad, for applying reciprocating forces to the ground and sensor means for generating a feedback signal representative of the force applied to the ground. Circuitry is provided for generating a pilot signal representative of the desired force to be applied to the ground. The pilot and feedback signals are single sideband shifted to increase both frequencies by a predetermined frequency. The high frequency pilot and feedback signals have their phase difference conventionally detected and provided to a digital computer for phase shifting the signal for controlling the vibrator so that the feedback signal is in phase with the pilot signal. In another embodiment, the instantaneous phase of each signal is computed continuously by a digital computer. The control signal digital representation is corrected to correspond with the pilot digital representation and an analog output signal is generated to provide the proper analog control signal.

Abstract: A remotely controlled circuit control device has first and second load contact assemblies movable into circuit engagement and circuit disengagement positions relative to one another in which one load contact assembly is operatively connected to a solenoid so that alternate forward strokes of the solenoid moves the one load contact assembly between reset and tripped positions through a push-push mechanism having an indexing portion and a latching portion. An overload mechanism cooperates with the latch portion to cause the load contact assemblies to move to the circuit disengaged position upon occurrence of a fault condition. The second load contact assembly includes pivotably mounted contact members which are linked to the first load contact assembly in such a way that circuit engagement during solenoid energization is precluded.

Abstract: Individual display modules are located along a shelf containing items for sale. The display modules are loaded via a hand-held unit with data pertaining to the items. This data has previously been downloaded from a host computer into the hand-held unit. In order to minimize human error, the hand-held unit contains a reader for reading a code from either the item or the shelf upon which the item is located. This code is then used by the hand-held unit in order to determine what data is to be downloaded into the appropriate display module. The coupling between the hand-held unit and the display modules may be of the type requiring a direct electrical connection or the close-proximity type employing optical or electro-magnetic coupling.

Abstract: A new process for plasma etching silicon oxides in integrated circuit structures. A chemistry comprising both oxygen and nitrogen trifluoride is used, with oxygen the dominant component. This provides excellent selectivity to silicon. This etch chemistry also erodes photoresist rapidly, so that it is typically used in combination with a hard-masking process. One particular application of this invention is in a cantilever-etch-mask contact profiling process.

Abstract: An analog signal conditioning and digitizing integrated circuit is provided having a multiplying digital to analog converter means (MDAC) including a gain capacitor array and an offset capacitor array, an operational amplifier, a feedback circuit including a feedback capacitor and a feedback clamping transistor, the operational amplifier and feedback circuit connected to the gain and offset capacitor arrays for setting the gain and the amount of offset correction of the MDAC, a correlated double sample circuit including a series capacitor connected to the operational amplifier and a series clamping transistor connected to the junction of the series capacitor and a buffer amplifier for sampling the noise to be substracted and/or nulled across the series capacitor, and an analog to digital converter operatively connected to the MDAC for digitizing the output of the MDAC.

Abstract: The disclosure relates to a photodetector, primarily for use in the infrared range, wherein a portion of the metal layer forming the gate is eliminated, resulting in no metal absorption loss and no differential tunnel breakdown. The system operates by establishing a fixed charge density at the semiconductor-insulator interface to create near flat band voltage in the open or hole area. No potential well is formed under the hole in the gate to collect charge so the metal gate formed around the hole controls the surface potential. Carriers generated in the hole area diffuse and drift to the potential wells created beneath the thick metal gate which surrounds the hole.

Abstract: A video system has a processor processing of data to be displayed on a CRT monitor. A memory which is the embodiment shown is a multiport dynamic random accessed memory, stores the data therein according to X and Y coordinates. A video controller controls the transfer of data between the processor and the memory; the controller also, has included therein an X and Y address logic for providing the X and Y coordinates to the memory.

Abstract: A semiconductor dynamic read/write memory of the multiplexed-address type employs an on-chip refresh counter which is activated by CAS-before-RAS sequence. This counter is made up of stages almost identical to the row address buffers so the same clocks can be used. Either the address input buffers or the refresh counter stages are gated into second-stage row address buffers, and carry feedback from these second stage buffers to the counter stages is used to increment the counter. The access time of the memory for normal read or write is not degraded by the refresh circuitry.

Abstract: An oscillator for an integrated circuit which includes a Schmitt trigger having an upper threshold voltage V.sub.H and a lower threshold voltage V.sub.L, a capacitor coupled between an input to the trigger and ground, a current generator coupled to the trigger input for charging the capacitor at a constant rate and a current generator coupled to the trigger input for discharging the capacitor at a constant rate. A charge switch in series with the charging current generator reversibly couples the charging current generator between a source of high voltage and the trigger input in response to a change in state of the trigger from a first state to a second state. A discharge switch in series with the discharging current generator reversibly couples the latter across the capacitor in response to a change in state of the trigger from the second state to the first state.

Abstract: Airborne navigation and communication systems are disclosed including a VOR/LOC (VHR Omnirange/Localizer) receiver and a communication transceiver each with separate control and display panels. Each panel includes a ten push-button press keys numbered 0-9, a function controller for operating mode selection and general control, a pair of digital displays (5 digits each) for displaying keyboard channel selection including an active channel and a standby channel and additional data, three function press keys--one for switching a standby channel into the active channel or vice versa or resetting the timer or changing the digital bearing display from "TO" to "FROM", a second key for either recalling a channel or backing up to a digit for correction during data entry, and a third key for storing frequency in memory locations or entering data.

Abstract: A dRAM cell and array of cells, together with a method of fabrication, are disclosed wherein the cell includes one field effect transistor and one capacitor with both the transistor and the capacitor formed in a trench in a substrate. One capacitor plate and the transistor source are common and are formed in the lower portion of the trench sidewall. The transistor drain is formed in the upper portion of the trench sidewall to connect to a bit line on the substrate surface, and the channel is the vertical portion of the trench sidewall between the source and drain. A ground line runs past the transistor gate in the upper portion of the trench down into the lower portion of the trench to form the other capacitor plate.

Abstract: A mounting substrate (10) is formed from a platelet of graphite (22) conformally coated with a layer of silicon carbide (24). A layer of silicon dioxide (25) is disposed thereon and a chip (16) mounted onto the substrate (10). The silicon carbide has a thermal expansion coefficient that is essentially equal to silicon in addition to a high thermal conductivity.

Abstract: A microcomputer device contains a CPU with an arithmetic/logic unit and data/address registers on a single semiconductor integrated circuit having a combined on - chip read/write memory for macrocode and microcode storage. A macrocode word is fetched from the memory and stored in an instruction register in the CPU, then a sequence of microcode words is fetched from the same memory based on this macrocode word. Both macrocode and microcode may be loaded into the combined memory from external to the chip, so the functions of the microcomputer may be changed for different tasks. The content of both microcode and macrocode, as well as the ratio of macrocode to microcode, can be varied by programming without any change in the circuitry of the chip.

Abstract: An MOS integrated circuit has an array of terminal means connectable to an output buffer or the like arranged around an array of MOS circuit components such as shift registers or the like and has a novel metal programmable matrix arranged for compactly and economically accommodating any selected interconnection of the shift registers and terminal pins at the metal conductor level of the integrated circuit.

Abstract: A CCD imager having one or more serial output shift registers 16, wherein the dark reference area 10 prime at the edge of the image area 10 is located so that it will be clocked into the opposite end 16 prime of the serial shift register 16 from the output amplifier 18. After a line of image information is clocked through the output amplifier 18, the dark reference information is left in dummy pixel area 16 double prime. At the next line transfer, the dark reference information stored in the portion 16 double prime is the first clocked into the output amplifier 18, and thus provides the reference information.Standard TV formats have a limited amount of time available for horizontal blanking; this time limit, together with the CCD well clock rate, restricts the number of CCD wells which can separate the amplifier from the edge of the array.

Abstract: A semiconductor memory circuit includes memory arrays (10), (12), (14) and (16). Each of the memory arrays has associated therewith shift registers (34), (36), (38) and (40). Transfer gates (54) are disposed between the memory arrays and the associated shift registers. A control circuit (69) is provided for receiving an external transfer signal and transferring the data between the arrays and the associated shift registers. The shift registers are clocked in response to receiving an external shift clock signal to serially output data therefrom. A delay circuit (292) is provided for delaying shifting of data for a predetermined duration to ensure that a complete transfer of data has been effected. Transfer of data is inhibited until the occurrence of the XBOOT signal by circuit (296) to provide for early occurrence of the transfer signal. Data access is maintained by a delay circuit (330) to accommodate late occurrence of the transfer signal by delaying the internal row address strobe.